Riccardo Tedeschi

Orcid: 0009-0007-4483-9261

According to our database1, Riccardo Tedeschi authored at least 6 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture.
CoRR, May, 2025

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing.
CoRR, March, 2025

HMR-NEureka: Hybrid Modular Redundancy DNN Acceleration in Heterogeneous RISC-V SoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution.
Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025

2024
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor.
CoRR, 2024

2023
Minimizing user inconvenience and operational costs in a dial-a-flight problem for flying safaris.
INFOR Inf. Syst. Oper. Res., January, 2023


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