César Fuguet Tortolero

According to our database, César Fuguet Tortolero authored at least 12 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores.

César Fuguet Tortolero

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor.

Yves Durand, Eric Guthmuller, César Fuguet Tortolero, Jérôme Fereyre, Andrea Bocco, Riccardo Alidori

Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022

2021

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

IEEE J. Solid State Circuits, 2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.

Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm² Inter-Chiplet Interconnects and 156mW/mm²@ 82%-Peak-Efficiency DC-DC Converters.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.

Yvain Thonnart, Stéphane Bernabé, Jean Charbonnier, Christian Bernard, David Coriat, César Fuguet Tortolero, Pierre Tissier, Benoît Charbonnier, Stéphane Malhouitre, Damien Saint-Patrice, Myriam Assous, Aditya Narayan, Ayse K. Coskun, Denis Dutoit, Pascal Vivet

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs.

Aditya Narayan, Yvain Thonnart, Pascal Vivet, César Fuguet Tortolero, Ayse K. Coskun

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.

Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017

Trace-driven exploration of sharing set management strategies for cache coherence in manycores.

Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems.

Yves Durand, Christian Bernard, Romain Lemaire, César Fuguet Tortolero, Emilie Garat

Proceedings of the Euromicro Conference on Digital System Design, 2017

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols.

Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot

Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2015

Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. (Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente).

César Fuguet Tortolero

PhD thesis, 2015