Richard B. Wunderlich

According to our database1, Richard B. Wunderlich authored at least 12 papers between 2005 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Single-Objective Path Planning for Autonomous Robots Using Reconfigurable Analog VLSI.
IEEE Trans. Syst. Man Cybern. Syst., 2017

2016
A Programmable and Configurable Mixed-Mode FPAA SoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2014
Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.
PhD thesis, 2014

Adaptive Floating-Gate Circuit Enabled Large-Scale FPAA.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Three dimensional robot path planning using a field programmable analog array.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Floating Gate-Based Field Programmable Mixed-Signal Array.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Neuron Array With Plastic Synapses and Programmable Dendrites.
IEEE Trans. Biomed. Circuits Syst., 2013

A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena.
IEEE Trans. Biomed. Circuits Syst., 2013

A large-scale FPAA enabling adaptive floating-gate circuits.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2009
Passgate Resistance Estimation based on the Compact EKV Model and Effective Mobility.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007
Capacitively-Biased Floating-Gate CMOS: a New Logic Family.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
Programmable floating-gate techniques for CMOS inverters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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