W. Robert Daasch

According to our database, W. Robert Daasch authored at least 39 papers between 1987 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Consistency in wafer based outlier screening.

Sebastian Siatkowski, Chuanhe Jay Shan, Li-C. Wang, Nikolas Sumikawa, W. Robert Daasch, John M. Carulli

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

What we know after twelve years developing and deploying test data analytics solutions.

Kenneth M. Butler, Amit Nahar, W. Robert Daasch

Proceedings of the 2016 IEEE International Test Conference, 2016

2015

Generalization of an outlier model into a "global" perspective.

Sebastian Siatkowski, Chia-Ling Chang, Li-C. Wang, Nikolas Sumikawa, LeRoy Winemberg, W. Robert Daasch

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

Copula Models of Correlation: A DRAM Case Study.

C. Glenn Shirley, W. Robert Daasch

IEEE Trans. Computers, 2014

Board manufacturing test correlation to IC manufacturing test.

C. Glenn Shirley, W. Robert Daasch, Phil Nigh, Zoe Conroy

Proceedings of the 2014 International Test Conference, 2014

2011

Die-level adaptive test: Real-time test reordering and elimination.

Kapil R. Gotkhindikar, W. Robert Daasch, Kenneth M. Butler, John M. Carulli Jr., Amit Nahar

Proceedings of the 2011 IEEE International Test Conference, 2011

2009

Statistics in Semiconductor Test: Going beyond Yield.

W. Robert Daasch, C. Glenn Shirley, Amit Nahar

IEEE Des. Test Comput., 2009

Multidimensional Test Escape Rate Modeling.

Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena, Amit Nahar, W. Robert Daasch

IEEE Des. Test Comput., 2009

Application of non-parametric statistics of the parametric response for defect diagnosis.

Rama Gudavalli, W. Robert Daasch, Phil Nigh, Douglas Heaberlin

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

Analyzing the Impact of Fault Tolerant BIST for VLSI Design.

Saurabh Jain, W. Robert Daasch, David Armbrust

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Silicon evaluation of longest path avoidance testing for small delay defects.

Ritesh P. Turakhia, W. Robert Daasch, Mark Ward, John Van Slyke

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers.

Ritesh P. Turakhia, W. Robert Daasch, Joel Lurkins, Brady Benware

IEEE Des. Test Comput., 2006

2005

Defect Screening Using Independent Component Analysis on I_DDQ.

Ritesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Burn-in reduction using principal component analysis.

Amit Nahar, W. Robert Daasch, Suresh Subramaniam

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

The value of statistical testing for quality, yield and test cost improvement.

Robert Madge, Brady Benware, Mark Ward, W. Robert Daasch

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Data-driven models for statistical testing: measurements, estimates and residuals.

W. Robert Daasch, Robert Madge

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Variance reduction and outliers: statistical analysis of semiconductor test data.

W. Robert Daasch, Robert Madge

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Detection of Temperature Sensitive Defects Using ZTC.

Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Minimum Testing Requirements to Screen Temperature Dependent Defects.

Chris Schuermyer, Jens Ruffler, W. Robert Daasch

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost.

Robert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Dude! Where's my data? - Cracking Open the Hermetically Sealed Tester.

W. Robert Daasch, Manu Rehani

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A radio-frequency CMOS active inductor and its application in designing high-Q filters.

Haiqiao Xiao, Rolf Schaumann, W. Robert Daasch, Phillip K. Wong, Branimir Pejcinovic

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs.

Robert Madge, Brady Benware, W. Robert Daasch

IEEE Des. Test Comput., 2003

Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs.

Brady Benware, Robert Madge, Cam Lu, W. Robert Daasch

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ.

Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.

Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins

IEEE Des. Test Comput., 2002

Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort.

W. Robert Daasch, James McNames, Robert Madge, Kevin Cota

IEEE Des. Test Comput., 2002

Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies.

Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Isolating and Removing Sources of Variation in Test Data.

David Turner, David Abercrombie, James McNames, W. Robert Daasch, Robert Madge

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Screening MinVDD Outliers Using Feed-Forward Voltage Testing.

Robert Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, W. Robert Daasch, Chris Schuermyer, C. Taylor, David Turner

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data.

W. Robert Daasch, Kevin Cota, James McNames, Robert Madge

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A Thermal-Aware Superscalar Microprocessor (invited).

Chee How Lim, W. Robert Daasch, George Cai

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

Neighbor selection for variance reduction in I_DDQ and other parametric data.

W. Robert Daasch, Kevin Cota, James McNames, Robert Madge

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

TEM²P²EST: A Thermal Enabled Multi-model Power/Performance ESTimator.

Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch

Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Variance reduction using wafer patterns in I_ddQ data.

W. Robert Daasch, James McNames, Daniel Bockelman, Kevin Cota

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1995

Accurate Predictions of Parallel Program Execution Time.

Michael A. Driscoll, W. Robert Daasch

J. Parallel Distributed Comput., 1995

1993

A 20 MHz Fully-balanced Transconductance-C Filter in 2 µm CMOS Technology.

Pan Wu, Rolf Schaumann, W. Robert Daasch

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

Automation of the ic layout of continuous-time transconductance-capacitor filters.

W. Robert Daasch, Martine Wedlake, Rolf Schaumann, Pan Wu

Int. J. Circuit Theory Appl., 1992

1987

High Speed Interconnection Using the Clos Network.

William A. Payne III, Fillia Makedon, W. Robert Daasch

Proceedings of the Supercomputing, 1987