Romain Dolbeau

According to our database, Romain Dolbeau authored at least 8 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores.

Antoni Portero, Carlos Falquez, Nam Ho, Polydoros Petrakis, Stepan Nassyr, Manolis Marazakis, Romain Dolbeau, Jorge Alejandro Nocua Cifuentes, Luis Bertran Alvarez, Dirk Pleiter, Estela Suarez

Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

2022

Correction to: Theoretical peak FLOPS per instruction set: a tutorial.

Romain Dolbeau

J. Supercomput., 2022

2021

Multilevel simulation-based co-design of next generation HPC microprocessors.

Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau

Proceedings of the 2021 International Workshop on Performance Modeling, 2021

2018

Theoretical peak FLOPS per instruction set: a tutorial.

Romain Dolbeau

J. Supercomput., 2018

2016

On the efficiency of the accelerated processing unit for scientific computing.

Issam Said, Pierre Fortin, Jean Luc Lamotte, Romain Dolbeau, Henri Calandra

Proceedings of the 24th High Performance Computing Symposium, 2016

2014

Automated Code Generation for Lattice Quantum Chromodynamics and beyond.

Denis Barthou, Olivier Brand-Foissac, Romain Dolbeau, Gilbert Grosdidier, Christine Eisenbeis, Michael Kruse, Olivier Pène, Konstantin Petrov, Claude Tadonki

CoRR, 2014

2013

Evaluation of Successive CPUs/APUs/GPUs Based on an OpenCL Finite Difference Stencil.

Henri Calandra, Romain Dolbeau, Pierre Fortin, Jean Luc Lamotte, Issam Said

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

2004

CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors.

Romain Dolbeau, André Seznec

J. Instr. Level Parallelism, 2004