Christine Eisenbeis

According to our database1, Christine Eisenbeis authored at least 44 papers between 1988 and 2017.

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Bibliography

2017
Dohko: an autonomic system for provision, configuration, and management of inter-cloud environments based on a software product line engineering method.
Clust. Comput., 2017

Accelerating Lattice Quantum Chromodynamics Simulations with Value Prediction.
Proceedings of the 2017 IEEE 7th International Symposium on Cloud and Service Computing, 2017

2016
Power-aware server consolidation for federated clouds.
Concurr. Comput. Pract. Exp., 2016

Autonomic Provisioning, Configuration, and Management of Inter-cloud Environments Based on a Software Product Line Engineering Method.
Proceedings of the 2016 International Conference on Cloud and Autonomic Computing, 2016

2015
Automating Resource Selection and Configuration in Inter-clouds through a Software Product Line Method.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

2014
Impact of Reverse Computing on Information Locality in Register Allocation for High Performance Computing.
Int. J. Parallel Program., 2014

Automated Code Generation for Lattice Quantum Chromodynamics and beyond.
CoRR, 2014

A Fine-grained Approach for Power Consumption Analysis and Prediction.
Proceedings of the International Conference on Computational Science, 2014

Excalibur: an autonomic cloud architecture for executing parallel applications.
Proceedings of the Fourth International Workshop on Cloud Data and Platforms, 2014

2011
Value Prediction and Speculative Execution on GPU.
Int. J. Parallel Program., 2011

High Performance by Exploiting Information Locality through Reverse Computing.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

Rematerialization-based register allocation through reverse computing.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Speculative Execution on GPU: An Exploratory Study.
Proceedings of the 39th International Conference on Parallel Processing, 2010

A Theoretical Framework for Value Prediction in Parallel Systems.
Proceedings of the 39th International Conference on Parallel Processing, 2010

2009
Spatial complexity of reversibly computable DAG.
Proceedings of the 2009 International Conference on Compilers, 2009

2007
Programming self developing blob machines for spatial computing..
Proceedings of the Fair Division, 24.06. - 29.06.2007, 2007

2006
<i>N</i>-synchronous Kahn networks: a relaxed model of synchrony for real-time systems.
Proceedings of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2006

2005
Synchronization of periodic clocks.
Proceedings of the EMSOFT 2005, 2005

2004
Early Periodic Register Allocation on ILP Processors.
Parallel Process. Lett., 2004

2003
Early Control of Register Pressure for Software Pipelined Loops.
Proceedings of the Compiler Construction, 12th International Conference, 2003

2002
Circular-arc graph coloring: On chords and circuits in the meeting graph.
Eur. J. Oper. Res., 2002

2001
Topic 08+13: Instruction-Level Parallelism and Computer Architecture.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000
Load-store optimization for software pipelining.
SIGARCH Comput. Archit. News, 2000

Handling Global Constraints in Compiler Strategy.
Int. J. Parallel Program., 2000

1999
On a Graph-theoretical Model for Cyclic Register Allocation.
Discret. Appl. Math., 1999

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Efficient implementation of the row-column 8×8 IDCT on VLIW architectures.
Proceedings of the 9th European Signal Processing Conference, 1998


A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops.
Proceedings of the Compiler Construction, 7th International Conference, 1998

1997

1995
The meeting graph: a new model for loop cyclic register allocation.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

Allocating registers in multiple instruction-issuing processors.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994
A strategy for array management in local memory.
Math. Program., 1994

Using timed Petri net to model instruction-level loop scheduling with resource constraints.
J. Comput. Sci. Technol., 1994

Decomposed software pipelining: A new perspective and a new approach.
Int. J. Parallel Program., 1994

Software pipelining with register allocation and spilling.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

Trace Software Pipelining: A Novel Technique for Parallelization of Loops with Branches.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

1993
Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop Programs.
Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993

Fast Enumeration of Solutions for Data Dependence Analysis and Data Locality Optimization.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992
A general algorithm for data dependence analysis.
Proceedings of the 6th international conference on Supercomputing, 1992

1991
A Quantitative Algorithm for Data Locality Optimization.
Proceedings of the Code Generation, 1991

1990
Compiler Techniques for Optimizing Memory and Register Usage on the Cray 2.
Int. J. High Speed Comput., 1990

1988
Squeezing more CPU performance out of a Cray-2 by Vector block scheduling.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

Optimization of horizontal microcode generation for loop structures.
Proceedings of the 2nd international conference on Supercomputing, 1988


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