Nam Ho

According to our database1, Nam Ho authored at least 10 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
FPGA-based reconfigurable cache mapping schemes: design and optimization.
PhD thesis, 2018

2017
Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
Proceedings of the International Conference on Field Programmable Technology, 2017

Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2015
Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enhancing an x86_64 multi-core architecture with data-flow execution support.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2010
MemMON: run-time off-chip detection for memory access violation in embedded systems.
Proceedings of the 2010 Symposium on Information and Communication Technology, 2010


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