Rutuparna Tamhankar

According to our database, Rutuparna Tamhankar authored at least 4 papers between 2005 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

Timing-Error-Tolerant Network-on-Chip Design Methodology.

Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips.

Srinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini, Giovanni De Micheli

Proceedings of the International Symposium on System-on-Chip, 2006

2005

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.

Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli

IEEE Trans. Parallel Distributed Syst., 2005

Performance driven reliable link design for networks on chips.

Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005