Antonio Pullini

According to our database1, Antonio Pullini authored at least 51 papers between 2005 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits, 2022

2021
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR, 2021

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI.
Integr., 2020

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI.
CoRR, 2020

2019
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing.
IEEE J. Solid State Circuits, 2019

An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Energy Efficient E-Skin Embedded System for Real-Time Tactile Data Decoding.
J. Low Power Electron., 2018

Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

GAP-8: A RISC-V SoC for AI at the Edge of the IoT.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test, 2017

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

μDMA: An autonomous I/O subsystem for IoT end-nodes.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Energy Efficient System for Tactile Data Decoding Using an Ultra-Low Power Parallel Platform.
Proceedings of the New Generation of CAS, 2017

2016
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
J. Signal Process. Syst., 2016

A Dual Processor Energy-Efficient Platform with Multi-core Accelerator for Smart Sensing.
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2015
Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Exploring architectural heterogeneity in intelligent vision systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014
Energy-efficient vision on the PULP platform for ultra-low power parallel computing.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2014

A lightweight cryptographic system for implantable biosensors.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Sub-mW reconfigurable interface IC for electrochemical sensing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2012
Row-based FBB: A design-time optimization for post-silicon tunable circuits.
Microelectron. J., 2012

2011
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

2010
Automatic synthesis of near-threshold circuits with fine-grained performance tunability.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

3D NoCs - Unifying inter & intra chip communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Networks on Chips: from research to products.
Proceedings of the 47th Design Automation Conference, 2010

2009
A floorplan-aware interactive tool flow for NoC design and synthesis.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Physically clustered forward body biasing for variability compensation in nanometer CMOS design.
Proceedings of the Design, Automation and Test in Europe, 2009

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Network-on-Chip design and synthesis outlook.
Integr., 2008

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal sleep transistor synthesis under timing and area constraints.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Scalable Algorithmic Framework for Row-Based Power-Gating.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Bringing NoCs to 65 nm.
IEEE Micro, 2007

NoC Design and Implementation in 65nm Technology.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Timing-driven row-based power gating.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips.
Proceedings of the International Symposium on System-on-Chip, 2006

2005
Fault tolerance overhead in network-on-chip flow control schemes.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005


  Loading...