Federico Angiolini

According to our database1, Federico Angiolini authored at least 54 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging.
IEEE Trans. Biomed. Circuits Syst., 2018

Safe and Efficient Deployment of Data-Parallelizable Applications on Many-Core Platforms: Theory and Practice.
IEEE Des. Test, 2018

2017
Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging.
IEEE Trans. Biomed. Circuits Syst., 2017

1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Single-FPGA complete 3D and 2D medical ultrasound imager.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

Live demonstration: Inexpensive 1024-channel 3D telesonography system on FPGA.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Inexpensive 1024-channel 3D telesonography system on FPGA.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Raspberry Pi driven flow-injection system for electrochemical continuous monitoring platforms.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Single-FPGA 3D ultrasound beamformer.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Demo: Efficient delay and apodization for on-FPGA 3D ultrasound.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Tackling the bottleneck of delay tables in 3D ultrasound imaging.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs.
IEEE Trans. Ind. Informatics, 2013

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip.
IEEE Trans. Computers, 2013

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores.
Parallel Comput., 2013

2012
Quest for the ultimate network-on-chip: the NaNoC project.
Proceedings of the 2012 Interconnection Network Architecture, 2012

2011
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

2010
Networks on Chips: from research to products.
Proceedings of the 47th Design Automation Conference, 2010

Exploring programming model-driven QoS support for NoC-based platforms.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
A floorplan-aware interactive tool flow for NoC design and synthesis.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A method for calculating hard QoS guarantees for Networks-on-Chip.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Synthesis of low-overhead configurable source routing tables for network interfaces.
Proceedings of the Design, Automation and Test in Europe, 2009

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
A Reactive and Cycle-True IP Emulator for MPSoC Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Network-on-Chip design and synthesis outlook.
Integr., 2008

Exploring architectural solutions for energy optimisations in bus-based system-on-chip.
IET Comput. Digit. Tech., 2008

Developing Mesochronous Synchronizers to Enable 3D NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Area and Power Modeling for Networks-on-Chip with Layout Awareness.
VLSI Design, 2007

Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Bringing NoCs to 65 nm.
IEEE Micro, 2007

NoC Design and Implementation in 65nm Technology.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Interactive presentation: Improving the fault tolerance of nanometric PLA designs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Designing Routing and Message-Dependent Deadlock Free Networks on Chips.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Area and Power Modeling Methodologies for Networks-on-Chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips.
Proceedings of the International Symposium on System-on-Chip, 2006

Reliability Support for On-Chip Memories Using Networks-on-Chip.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Designing application-specific networks on chips with floorplan information.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Contrasting a NoC and a traditional interconnect fabric with layout awareness.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

An integrated open framework for heterogeneous MPSoC design space exploration.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
An efficient profile-based algorithm for scratchpad memory partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Traffic Injection Methodology with Support for System-Level Synchronization.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Simultaneous memory and bus partitioning for SoC architectures.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Fault tolerance overhead in network-on-chip flow control schemes.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Networks on Chips: A Synthesis Perspective.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.
Proceedings of the 2005 Design, 2005

A Network Traffic Generator Model for Fast Network-on-Chip Simulation.
Proceedings of the 2005 Design, 2005

2004
Analyzing On-Chip Communication in a MPSoC Environment.
Proceedings of the 2004 Design, 2004

A post-compiler approach to scratchpad mapping of code.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Polynomial-time algorithm for on-chip scratchpad memory partitioning.
Proceedings of the International Conference on Compilers, 2003


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