Ryan Huang

According to our database1, Ryan Huang authored at least 12 papers between 2012 and 2026.

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Timeline

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Bibliography

2026
Atomic Information Flow: A Network Flow Model for Tool Attributions in RAG Systems.
CoRR, February, 2026

Resilient Infrastructures via Digital Unification.
Commun. ACM, January, 2026

2020
Observations on Porting In-memory KV stores to Persistent Memory.
CoRR, 2020

2017
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A self-adaptive write driver with fast termination of step-up pulse for ReRAM.
IEICE Electron. Express, 2016

2015
A low cost and high reliability true random number generator based on resistive random access memory.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
A 0.13 µm 8 Mb Logic-Based Cu<sub>x</sub> Si<sub>y</sub> O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction.
IEEE J. Solid State Circuits, 2013

A 2Mb ReRAM with two bits error correction codes circuit for high reliability application.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Variation-tolerant Cu<sub>x</sub>Si<sub>y</sub>O-based RRAM for low power application.
IEICE Electron. Express, 2012


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