Xiaoyong Xue

Orcid: 0000-0001-9001-4569

According to our database1, Xiaoyong Xue authored at least 60 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

HashC: Making deep learning coverage testing finer and faster.
J. Syst. Archit., November, 2023

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2023

MedTiny: Enhanced Mediator Modeling Language for Scalable Parallel Algorithms.
Proceedings of the 23rd IEEE International Conference on Software Quality, 2023

A 9Mb HZO-Based Embedded FeRAM with 10<sup>12</sup>-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

NBSSN: A Neuromorphic Binary Single-Spike Neural Network for Efficient Edge Intelligence.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Branch and Bound for Sigmoid-Like Neural Network Verification.
Proceedings of the Formal Methods and Software Engineering, 2023

kProp: Multi-neuron Relaxation Method for Neural Network Robustness Verification.
Proceedings of the Fundamentals of Software Engineering - 10th International Conference, 2023

2022
A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications.
Microelectron. J., 2022

A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices.
Microelectron. J., 2022

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

HashC: Making DNNs' Coverage Testing Finer and Faster.
Proceedings of the Dependable Software Engineering. Theories, Tools, and Applications, 2022

NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications.
IEEE J. Solid State Circuits, 2021

Orthogonal obfuscation based key management for multiple IP protection.
Integr., 2021

24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m<sup>2</sup> Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Fast Style Transfer with High Shape Retention.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Combining Max Pooling and ReLU Activation Function in Stochastic Computing.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Arbitrary Style Transfer via Learning to Paint in the Feature Domain.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Novel 15T SRAM Cell for Low Voltage High Reliability Application.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm<sup>2</sup> using Sneaking Current Suppression and Compensation Techniques.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Parallel Change Detection Method for Spatiotemporally Multi-Temporal SAR Image Based On Enhance Learning and Wavelet.
Proceedings of the 13th International Symposium on Computational Intelligence and Design, 2020

Directly Obtaining Matching Points without Keypoints for Image Stitching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique.
IEICE Electron. Express, 2019

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Orthogonal Algorithm for Key Management in Hardware Obfuscation.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
An Automatic Task Partition Method for Multi-core System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAM.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F<sup>2</sup> and K-means Clustering for Power Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Distributed graph database as base of smart world things.
Proceedings of the 2017 IEEE SmartWorld, 2017

A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 1.0-3.0GHz LTE transmitter with CIM enhancement.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A self-adaptive write driver with fast termination of step-up pulse for ReRAM.
IEICE Electron. Express, 2016

A Distributed Graph Database for the Data Management of IoT Systems.
Proceedings of the 2016 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2016

Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low cost and high reliability true random number generator based on resistive random access memory.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
A 0.13 µm 8 Mb Logic-Based Cu<sub>x</sub> Si<sub>y</sub> O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction.
IEEE J. Solid State Circuits, 2013

A 2Mb ReRAM with two bits error correction codes circuit for high reliability application.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage.
IEICE Electron. Express, 2012

A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Novel 2T programmable element to improve density and performance of FPGA.
IEICE Electron. Express, 2011

Novel RRAM programming technology for instant-on and high-security FPGAs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell.
IEICE Trans. Electron., 2010


  Loading...