Saburo Muroga

According to our database1, Saburo Muroga authored at least 71 papers between 1957 and 1999.

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Awards

IEEE Fellow

IEEE Fellow 1977, "".

Timeline

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Bibliography

1999
Logic Synthesizer with Optimizations in Two Phases.
Proceedings of the VLSI Handbook., 1999

Pass Transistors.
Proceedings of the VLSI Handbook., 1999

Adders.
Proceedings of the VLSI Handbook., 1999

Dividers.
Proceedings of the VLSI Handbook., 1999

Multipliers.
Proceedings of the VLSI Handbook., 1999

Logic Synthesis with AND and OR Gates in Multi-levels.
Proceedings of the VLSI Handbook., 1999

Field-Programmable Gate Arrays.
Proceedings of the VLSI Handbook., 1999

Cell-Library Design Approach.
Proceedings of the VLSI Handbook., 1999

Field-Programmable Gate Arrays.
Proceedings of the VLSI Handbook., 1999

Mask-Programmable Gate Arrays.
Proceedings of the VLSI Handbook., 1999

Programmable Logic Devices.
Proceedings of the VLSI Handbook., 1999

Full-Custom and Semi-Custom Design.
Proceedings of the VLSI Handbook., 1999

CMOS.
Proceedings of the VLSI Handbook., 1999

Emitter-Coupled Logic.
Proceedings of the VLSI Handbook., 1999

Logic Synthesizer by the Transduction Method.
Proceedings of the VLSI Handbook., 1999

Logic Synthesis with a Minimum Number of Negative Gates.
Proceedings of the VLSI Handbook., 1999

Logic Synthesis with NAND (or NOR) Gates in Multi-levels.
Proceedings of the VLSI Handbook., 1999

Logic Properties of Transistor Circuits.
Proceedings of the VLSI Handbook., 1999

Sequential Networks with AND and OR Gates.
Proceedings of the VLSI Handbook., 1999

Logic Synthesis with AND and OR Gates in Two Levels.
Proceedings of the VLSI Handbook., 1999

Simplification of Logic Expressions.
Proceedings of the VLSI Handbook., 1999

Basic Theory of Logic Functions.
Proceedings of the VLSI Handbook., 1999

Expressions of Logic Functions.
Proceedings of the VLSI Handbook., 1999

Binary Decision Diagrams.
Proceedings of the VLSI Handbook., 1999

1996
Optimization methods for look-up table-type FPGAs based on permissible functions.
Systems and Computers in Japan, 1996

Design of logic circuits with wired-logic utilizing transduction method.
Systems and Computers in Japan, 1996

1995
Optimization methods for lookup-table-based FPGAs using transduction method.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993
A Shared Memory Parallel Algorithm for Logic Synthesis.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1991
Absolute Minimization of Completely Specified Switching Functions.
IEEE Trans. Computers, 1991

Computer-Aided Logic Synthesis for VLSI Chips.
Advances in Computers, 1991

Logic Optimization of MOS Networks.
Proceedings of the 28th Design Automation Conference, 1991

A Resynthesis Approach for Network Optimization.
Proceedings of the 28th Design Automation Conference, 1991

1990
SYLON-REDUCE: an MOS network optimization algorithms using permissible functions.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Timing Optimization for Multi-Level Combinational Networks.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
The Transduction Method-Design of Logic Networks Based on Permissible Functions.
IEEE Trans. Computers, 1989

SYLON-DREAM: a multi-level network synthesizer.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Design of MOS networks in single-rail input logic for incompletely specified functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Input assignment algorithm for decoded-PLAs with multi-input decoders.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables.
IEEE Trans. Computers, 1987

Derivation of Minimal Sums for Completely Specified Functions.
IEEE Trans. Computers, 1987

1986
Properties of Wired Logic.
IEEE Trans. Computers, 1986

1985
Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables.
IEEE Trans. Computers, 1985

Minimal covering problem and PLA minimization.
International Journal of Parallel Programming, 1985

1984
Parallel multipliers with NOR gates based on G-minimum adders.
International Journal of Parallel Programming, 1984

1983
Parallel Binary Adders with a Minimum Number of Connections.
IEEE Trans. Computers, 1983

1982
Logic Networks of Carry-Save Adders.
IEEE Trans. Computers, 1982

1980
Useless prime implicants of incompletely specified multiple-output switching functions.
International Journal of Parallel Programming, 1980

1979
Minimum Parallel Binary Adders with NOR (NAND) Gates.
IEEE Trans. Computers, 1979

Comments on "Generalization of Consensus Theory and Application to the Minimization of Boolean Functions".
IEEE Trans. Computers, 1979

Comments on "Computing Irredundant Normal Forms from Abbreviated Presence Functions".
IEEE Trans. Computers, 1979

Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions.
IEEE Trans. Computers, 1979

1976
Minimization of Logic Networks Under a Generalized Cost Function.
IEEE Trans. Computers, 1976

1974
Optimal One-Bit Full Adders With Different Types of Gates.
IEEE Trans. Computers, 1974

Redundancy check technique for designing optimal networks by branch-and-bound method.
International Journal of Parallel Programming, 1974

1972
Design of Optimal Switching Networks by Integer Programming.
IEEE Trans. Computers, 1972

Optimal Networks of NOR-OR Gates for Functions of Three Variables.
IEEE Trans. Computers, 1972

An implicit enumeration program for zero-one integer programming.
International Journal of Parallel Programming, 1972

1971
Synthesis of Networks with a Minimum Number of Negative Gates.
IEEE Trans. Computers, 1971

Technical Note - Results in Using Gomory's All-Integer Integer Algorithm to Design Optimum Logic Networks.
Operations Research, 1971

Threshold logic and its applications.
Wiley, ISBN: 978-0-471-62530-8, 1971

1970
Adaptive Linear Classifier by Linear Programming.
IEEE Trans. Systems Science and Cybernetics, 1970

Enumeration of Threshold Functions of Eight Variables.
IEEE Trans. Computers, 1970

1966
Lower Bound of the Number of Threshold Functions.
IEEE Trans. Electronic Computers, 1966

1965
Lower Bounds of the Number of Threshold Functions and a Maximum Weight.
IEEE Trans. Electronic Computers, 1965

Generation and Asymmetry of Self-Dual Threshold Functions.
IEEE Trans. Electronic Computers, 1965

1962
Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight
Proceedings of the 3rd Annual Symposium on Switching Circuit Theory and Logical Design, 1962

1961
Functional forms of majority functions and a necessary and sufficient condition for their realizability
Proceedings of the 2nd Annual Symposium on Switching Circuit Theory and Logical Design, 1961

Two problems on threshold functions
Proceedings of the 2nd Annual Symposium on Switching Circuit Theory and Logical Design, 1961

1959
The Parametron Digital Computer MUSASINO-1.
IRE Trans. Electronic Computers, 1959

The principle of majority decision logical elements and the complexity of their circuits.
Proceedings of the Information Processing, 1959

1957
On the capacity of a noisy continuous channel.
IRE Trans. Information Theory, 1957


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