Sadahiro Tani

According to our database, Sadahiro Tani authored at least 10 papers between 1980 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning.

Yusaku Hirai, Toshimasa Matsuoka, Sadahiro Tani, Shodai Isami, Keiji Tatsumi, Masayuki Ueda, Takatsugu Kamata

IEEE Access, 2019

2017

Behavior-Level Analysis of a Successive Stochastic Approximation Analog-to-Digital Conversion System for Multi-Channel Biomedical Data Acquisition.

Sadahiro Tani, Toshimasa Matsuoka, Yusaku Hirai, Toshifumi Kurata, Keiji Tatsumi, Tomohiro Asano, Masayuki Ueda, Takatsugu Kamata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

An analog front-end employing 87 dB SNDR stochastic SAR-ADC for a biomedical sensor.

Takatsugu Kamata, Masayuki Ueda, Yusaku Hirai, Sadahiro Tani, Tomohiro Asano, Shodai Isami, Toshifumi Kurata, Keiji Tatsumi, Toshimasa Matsuoka

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A calibration with an adaptive data selection based on Bayes estimation for a successive stochastic approximation ADC system.

Keiji Tatsumi, Toshimasa Matsuoka, Sadahiro Tani

Proceedings of the Joint 17th World Congress of International Fuzzy Systems Association and 9th International Conference on Soft Computing and Intelligent Systems, 2017

2016

An offset distribution modification technique of stochastic flash ADC.

Tomohiro Asano, Yusaku Hirai, Sadahiro Tani, Shinya Yano, Ikkyun Jo, Toshimasa Matsuoka

IEICE Electron. Express, 2016

2005

Interconnect capacitance extraction for system LCD circuits.

Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2003

Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays.

Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

Parasitic capacitance modeling for multilevel interconnects.

Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

1981

A Layout System for the Random Logic Portion of an MOS LSI Chip.

Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki

IEEE Trans. Computers, 1981

1980

A layout system for the random logic portion of MOS LSI.

Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki

Proceedings of the 17th Design Automation Conference, 1980