Saleh Karman
Orcid: 0000-0002-7601-8827
According to our database1,
Saleh Karman
authored at least 9 papers
between 2019 and 2025.
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Bibliography
2025
34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2022
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
IEEE J. Solid State Circuits, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2019
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.
IEEE J. Solid State Circuits, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019