Daniel A. Jiménez

According to our database, Daniel A. Jiménez authored at least 85 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering.

Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching.

Daniel A. Jiménez, Elvira Teran, Paul V. Gratz

IEEE Comput. Archit. Lett., 2023

A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end.

Gino Chacon, Nathan Gober, Krishnendra Nathella, Paul V. Gratz, Daniel A. Jiménez

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Rebasing Microarchitectural Research with Industry Traces.

Josué Feliu, Arthur Perais, Daniel A. Jiménez, Alberto Ros

Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022

The Championship Simulator: Architectural Simulation for Education and Competition.

Nathan Gober, Gino Chacon, Lei Wang, Paul V. Gratz, Daniel A. Jiménez, Elvira Teran, Seth H. Pugsley, Jinchun Kim

CoRR, 2022

Dynamic Set Stealing to Improve Cache Performance.

Brady Testa, Samira Mirbagher Ajorpaz, Daniel A. Jiménez

Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

Page Size Aware Cache Prefetching.

Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jiménez, Marc Casas

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications.

Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A. Jiménez, Baris Kasikci

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Thermometer: profile-guided btb replacement for data center applications.

Shixin Song, Tanvir Ahmed Khan, Sara Mahdizadeh-Shahri, Akshitha Sriraman, Niranjan K. Soundararajan, Sreenivas Subramoney, Daniel A. Jiménez, Heiner Litz, Baris Kasikci

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Composite Instruction Prefetching.

Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul V. Gratz, Daniel A. Jiménez, Samira Mirbagher Ajorpaz

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches.

Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021

Top Picks From the 2020 Computer Architecture Conferences.

Daniel A. Jiménez

IEEE Micro, 2021

Morrigan: A Composite Instruction TLB Prefetcher.

Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jiménez, Marc Casas

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Exploiting Page Table Locality for Agile TLB Prefetching.

Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Daniel A. Jiménez, Marc Casas

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron.

Samira Mirbagher Ajorpaz, Gilles Pokam, Esmaeil Mohammadian Koruyeh, Elba Garza, Nael B. Abu-Ghazaleh, Daniel A. Jiménez

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

CHiRP: Control-Flow History Reuse Prediction.

Samira Mirbagher Ajorpaz, Elba Garza, Gilles Pokam, Daniel A. Jiménez

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Support for Diverse Students.

Daniel A. Jiménez

Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

Evolution of the Samsung Exynos CPU Microarchitecture.

Brian Grayson, Jeff Rupley, Gerald D. Zuraski, Eric Quinnell, Daniel A. Jiménez, Tarun Nakra, Paul Kitchin, Ryan Hensley, Edward Brekelbaum, Vikas Sinha, Ankit Ghiya

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Characterizing the impact of last-level cache replacement policies on big-data workloads.

Alexandre Valentin Jamet, Lluc Alvarez, Daniel A. Jiménez, Marc Casas

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors.

Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.

Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.

Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Daniel Ödman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber

CoRR, 2019

The impact of cache inclusion policies on cache management techniques.

Luna Backes, Daniel A. Jiménez

Proceedings of the International Symposium on Memory Systems, 2019

Bit-level perceptron prediction for indirect branches.

Elba Garza, Samira Mirbagher Ajorpaz, Tahsin Ahmad Khan, Daniel A. Jiménez

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Perceptron-based prefetch filtering.

Eshan Bhatia, Gino Chacon, Seth H. Pugsley, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez

Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018

MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors.

Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez

IEEE Comput. Archit. Lett., 2018

Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer.

Samira Mirbagher Ajorpaz, Elba Garza, Sangam Jindal, Daniel A. Jiménez

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Flexible associativity for DRAM caches.

Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson, Daniel A. Jiménez

Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017

Multiperspective reuse prediction.

Daniel A. Jiménez, Elvira Teran

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy.

Jinchun Kim, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez, Seth H. Pugsley, Chris Wilkerson

Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016

Sensible Energy Accounting with Abstract Metering for Multicore Systems.

Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero

ACM Trans. Archit. Code Optim., 2016

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.

Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie

Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Perceptron learning for reuse prediction.

Elvira Teran, Zhe Wang, Daniel A. Jiménez

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Minimal disturbance placement and promotion.

Elvira Teran, Yingying Tian, Zhe Wang, Daniel A. Jiménez

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

Adaptive GPU cache bypassing.

Yingying Tian, Sooraj Puthoor, Joseph L. Greathouse, Bradford M. Beckmann, Daniel A. Jiménez

Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015

2014

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip.

Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez

IEEE Trans. Computers, 2014

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors.

David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel A. Jiménez

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Last-level cache deduplication.

Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez, Gabriel H. Loh

Proceedings of the 2014 International Conference on Supercomputing, 2014

Adaptive placement and migration policy for an STT-RAM-based hybrid cache.

Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Improving cache performance using read-write partitioning.

Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, Daniel A. Jiménez

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

WADE: Writeback-aware dynamic cache management for NVM-based main memory system.

Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez

ACM Trans. Archit. Code Optim., 2013

Temporal-based multilevel correlating inclusive cache replacement.

Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez

ACM Trans. Archit. Code Optim., 2013

Insertion and promotion for tree-based PseudoLRU last-level caches.

Daniel A. Jiménez

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Improving multi-core performance using mixed-cell cache architecture.

Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, Daniel A. Jiménez

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors.

Reena Panda, Paul V. Gratz, Daniel A. Jiménez

IEEE Comput. Archit. Lett., 2012

Rank idle time prediction driven last-level cache writeback.

Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez

Proceedings of the 2012 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '12, 2012

Improving writeback efficiency with decoupled last-write prediction.

Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Decoupled dynamic cache segmentation.

Samira Manabi Khan, Zhe Wang, Daniel A. Jiménez

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

Reducing network-on-chip energy consumption through spatial locality speculation.

Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jiménez

Proceedings of the NOCS 2011, 2011

An optimized scaled neural branch predictor.

Daniel A. Jiménez

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback.

Zhe Wang, Daniel A. Jiménez

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Program Interferometry.

Zhe Wang, Daniel A. Jiménez

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy.

Yingying Tian, Daniel A. Jiménez

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Decoupled Cache Segmentation: Mutable Policy with Automated Bypass.

Samira Manabi Khan, Daniel A. Jiménez

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Sampling Dead Block Prediction for Last-Level Caches.

Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Insertion policy selection using Decision Tree Analysis.

Samira Manabi Khan, Daniel A. Jiménez

Proceedings of the 28th International Conference on Computer Design, 2010

Using dead blocks as a virtual victim cache.

Samira Manabi Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.

Chunling Hu, Daniel A. Jiménez, Ulrich Kremer

Trans. High Perform. Embed. Archit. Compil., 2009

Generalizing neural branch prediction.

Daniel A. Jiménez

ACM Trans. Archit. Code Optim., 2009

Mixed-Signal Approximate Computation: A Neural Predictor Case Study.

Renée St. Amant, Daniel A. Jiménez, Doug Burger

IEEE Micro, 2009

Composite Confidence Estimators for Enhanced Speculation Control.

Daniel A. Jiménez

Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

2008

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.

Gabriel H. Loh, Daniel A. Jiménez

Int. J. Parallel Program., 2008

Low-power, high-performance analog neural branch prediction.

Renée St. Amant, Daniel A. Jiménez, Doug Burger

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

A Two-Level Load/Store Queue Based on Execution Locality.

Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007

Guest Editor's Introduction.

Daniel A. Jiménez

J. Instr. Level Parallelism, 2007

An evaluation infrastructure for power and energy optimisations.

Chunling Hu, Daniel A. Jiménez, Ulrich Kremer

Int. J. Embed. Syst., 2007

Efficient Program Power Behavior Characterization.

Chunling Hu, Daniel A. Jiménez, Ulrich Kremer

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

A Flexible Heterogeneous Multi-Core Architecture.

Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors.

Daniel A. Jiménez, Gabriel H. Loh

Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

A decoupled KILO-instruction processor.

Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2005

Improved latency and accuracy for neural branch prediction.

Daniel A. Jiménez

ACM Trans. Comput. Syst., 2005

The Camino Compiler infrastructure.

Chunling Hu, John B. P. McCabe, Daniel A. Jiménez, Ulrich Kremer

SIGARCH Comput. Archit. News, 2005

Idealized Piecewise Linear Branch Prediction.

Daniel A. Jiménez

J. Instr. Level Parallelism, 2005

Chained In-Order/Out-of-Order DoubleCore Architecture.

Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez

Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

Code placement for improving dynamic branch prediction accuracy.

Daniel A. Jiménez

Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor.

Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Piecewise Linear Branch Prediction.

Daniel A. Jiménez

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Toward an Evaluation Infrastructure for Power and Energy Optimizations.

Chunling Hu, Daniel A. Jiménez, Ulrich Kremer

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Exploiting Procedure Level Locality to Reduce Instruction Cache Misses.

Ravi V. Batchu, Daniel A. Jiménez

Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003

Fast Path-Based Neural Branch Prediction.

Daniel A. Jiménez

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Reconsidering Complex Branch Predictors.

Daniel A. Jiménez

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002

Neural methods for dynamic branch prediction.

Daniel A. Jiménez, Calvin Lin

ACM Trans. Comput. Syst., 2002

2001

Dynamic Branch Prediction with Perceptrons.

Daniel A. Jiménez, Calvin Lin

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Boolean Formula-Based Branch Prediction for Future Technologies.

Daniel A. Jiménez, Heather L. Hanson, Calvin Lin

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000

The impact of delay on the design of branch predictors.

Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000