Daniel A. Jiménez

Affiliations:
  • Texas A&M University, College Station, TX, USA


According to our database1, Daniel A. Jiménez authored at least 74 papers between 2000 and 2021.

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Bibliography

2021
Top Picks From the 2020 Computer Architecture Conferences.
IEEE Micro, 2021

Morrigan: A Composite Instruction TLB Prefetcher.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Exploiting Page Table Locality for Agile TLB Prefetching.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

CHiRP: Control-Flow History Reuse Prediction.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Support for Diverse Students.
Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

Evolution of the Samsung Exynos CPU Microarchitecture.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Characterizing the impact of last-level cache replacement policies on big-data workloads.
Proceedings of the IEEE International Symposium on Workload Characterization, 2020

SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020


2019
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.
CoRR, 2019

The impact of cache inclusion policies on cache management techniques.
Proceedings of the International Symposium on Memory Systems, 2019

Bit-level perceptron prediction for indirect branches.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Perceptron-based prefetch filtering.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors.
IEEE Comput. Archit. Lett., 2018

Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Flexible associativity for DRAM caches.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
Multiperspective reuse prediction.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Sensible Energy Accounting with Abstract Metering for Multicore Systems.
ACM Trans. Archit. Code Optim., 2016

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Perceptron learning for reuse prediction.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Minimal disturbance placement and promotion.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Adaptive GPU cache bypassing.
Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015

2014
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip.
IEEE Trans. Computers, 2014

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Last-level cache deduplication.
Proceedings of the 2014 International Conference on Supercomputing, 2014

Adaptive placement and migration policy for an STT-RAM-based hybrid cache.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Improving cache performance using read-write partitioning.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
WADE: Writeback-aware dynamic cache management for NVM-based main memory system.
ACM Trans. Archit. Code Optim., 2013

Temporal-based multilevel correlating inclusive cache replacement.
ACM Trans. Archit. Code Optim., 2013

Insertion and promotion for tree-based PseudoLRU last-level caches.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Improving multi-core performance using mixed-cell cache architecture.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors.
IEEE Comput. Archit. Lett., 2012

Rank idle time prediction driven last-level cache writeback.
Proceedings of the 2012 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '12, 2012

Improving writeback efficiency with decoupled last-write prediction.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Decoupled dynamic cache segmentation.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
Reducing network-on-chip energy consumption through spatial locality speculation.
Proceedings of the NOCS 2011, 2011

An optimized scaled neural branch predictor.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Program Interferometry.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Decoupled Cache Segmentation: Mutable Policy with Automated Bypass.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Sampling Dead Block Prediction for Last-Level Caches.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Insertion policy selection using Decision Tree Analysis.
Proceedings of the 28th International Conference on Computer Design, 2010

Using dead blocks as a virtual victim cache.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.
Trans. High Perform. Embed. Archit. Compil., 2009

Generalizing neural branch prediction.
ACM Trans. Archit. Code Optim., 2009

Mixed-Signal Approximate Computation: A Neural Predictor Case Study.
IEEE Micro, 2009

Composite Confidence Estimators for Enhanced Speculation Control.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

2008
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.
Int. J. Parallel Program., 2008

Low-power, high-performance analog neural branch prediction.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

A Two-Level Load/Store Queue Based on Execution Locality.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Guest Editor's Introduction.
J. Instr. Level Parallelism, 2007

An evaluation infrastructure for power and energy optimisations.
Int. J. Embed. Syst., 2007

Efficient Program Power Behavior Characterization.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

A Flexible Heterogeneous Multi-Core Architecture.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors.
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

A decoupled KILO-instruction processor.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2005
Improved latency and accuracy for neural branch prediction.
ACM Trans. Comput. Syst., 2005

The Camino Compiler infrastructure.
SIGARCH Comput. Archit. News, 2005

Idealized Piecewise Linear Branch Prediction.
J. Instr. Level Parallelism, 2005

Chained In-Order/Out-of-Order DoubleCore Architecture.
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

Code placement for improving dynamic branch prediction accuracy.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Piecewise Linear Branch Prediction.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Toward an Evaluation Infrastructure for Power and Energy Optimizations.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Exploiting Procedure Level Locality to Reduce Instruction Cache Misses.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003
Fast Path-Based Neural Branch Prediction.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Reconsidering Complex Branch Predictors.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
Neural methods for dynamic branch prediction.
ACM Trans. Comput. Syst., 2002

2001
Dynamic Branch Prediction with Perceptrons.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Boolean Formula-Based Branch Prediction for Future Technologies.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000
The impact of delay on the design of branch predictors.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000


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