Sander Gierkink

According to our database1, Sander Gierkink authored at least 8 papers between 2004 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2009
A 3-level PWM ADSL2+ CO line driver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump.
IEEE J. Solid State Circuits, 2008

A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator.
IEEE J. Solid State Circuits, 2008

An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Process and Temperature Compensated Two-Stage Ring Oscillator.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 2.5Gb/s Burst-Mode CDR based on a 1/8<sup>th</sup> rate Dual Pulse Ring Oscillator.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2004
A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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