Sang-Hye Chung

According to our database1, Sang-Hye Chung authored at least 12 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015
A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13~µm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider.
IEEE Trans. Very Large Scale Integr. Syst., 2012

1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


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