Joo-Sun Choi

According to our database1, Joo-Sun Choi authored at least 34 papers between 2006 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2015
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits, 2015

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

5.7 A 29nW bandgap reference circuit.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
CMOS Charge Pump With No Reversion Loss and Enhanced Drivability.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.
Proceedings of the Symposium on VLSI Circuits, 2014

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.
IEEE J. Solid State Circuits, 2013

Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.
IEEE J. Solid State Circuits, 2012

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs.
IEICE Trans. Electron., 2011

A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


2010
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232].
IEEE J. Solid State Circuits, 2010

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.
IEEE J. Solid State Circuits, 2010

Silicon 3D-integration technology and systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


A highly reliable multi-cell antifuse scheme using DRAM cell capacitors.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.
IEEE J. Solid State Circuits, 2009

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits, 2009

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007

2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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