Sang Won Son

According to our database1, Sang Won Son authored at least 11 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Sound event detection based on auxiliary decoder and maximum probability aggregation for DCASE Challenge 2024 Task 4.
CoRR, 2024

2023
Semi-supervsied Learning-based Sound Event Detection using Freuqency Dynamic Convolution with Large Kernel Attention for DCASE Challenge 2023 Task 4.
CoRR, 2023

2022
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control.
IEEE J. Solid State Circuits, 2022

A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO.
IEEE J. Solid State Circuits, 2021

32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019
A 28-nm 75-fs<sub>rms</sub> Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction.
IEEE J. Solid State Circuits, 2019

2017
A 14-nm 0.14-ps<sub>rms</sub> Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration.
IEEE J. Solid State Circuits, 2017

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016


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