Santiago Remersaro

According to our database1, Santiago Remersaro authored at least 6 papers between 2004 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
A scalable method for the generation of small test sets.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Scan-Based Tests with Low Switching Activity.
IEEE Des. Test Comput., 2007

Low Shift and Capture Power Scan Tests.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.
Proceedings of the 2006 IEEE International Test Conference, 2006

2004
Analysis and improvements to MATE algorithm.
Proceedings of the 23rd IEEE International Performance Computing and Communications Conference, 2004


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