Thomas Rinderknecht

According to our database1, Thomas Rinderknecht authored at least 9 papers between 2003 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs.
Proceedings of the 22nd Asian Test Symposium, 2013

2008
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Programmable Scan-Based Logic Built-In Self Test.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Signature Based Diagnosis for Logic BIST.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Hardware Ef.cient LBISTWith Complementary Weights.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Logic BIST Using Constrained Scan Cells.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Embedded Test for Low Cost Manufacturing.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Logic BIST with Scan Chain Segmentation.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
High-Frequency, At-Speed Scan Testing.
IEEE Des. Test Comput., 2003


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