Ganesh Balamurugan

According to our database1, Ganesh Balamurugan authored at least 16 papers between 1999 and 2018.

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Bibliography

2018
A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2015
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.
J. Solid-State Circuits, 2014

2013
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.
J. Solid-State Circuits, 2013

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS.
J. Solid-State Circuits, 2010

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.
IEEE Trans. on Circuits and Systems, 2009

2008
Joint Equalization and Coding for On-Chip Bus Communication.
IEEE Trans. VLSI Syst., 2008

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Strong injection locking of low-Q LC oscillators.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Future Microprocessor Interfaces: Analysis, Design and Optimization.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
Joint Equalization and Coding for On-Chip Bus Communication.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

1999
Energy-efficient dynamic circuit design in the presence of crosstalk noise.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999


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