Scott Lerner

According to our database, Scott Lerner authored at least 15 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.

Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019

Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors.

Scott Lerner, Isikcan Yilmaz, Baris Taskin

IEEE Trans. Very Large Scale Integr. Syst., 2019

Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis.

Scott Lerner, Baris Taskin

IEEE Trans. Very Large Scale Integr. Syst., 2019

Robust Low Power Clock Synchronization for Multi-Die Systems.

Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Low Swing - Low Frequency Rotary Traveling Wave Oscillators.

Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement.

Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

NoC Router Lifetime Improvement using Per-Port Router Utilization.

Scott Lerner, Vasil Pano, Baris Taskin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis.

Scott Lerner, Baris Taskin

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

2017

Slew-down: analysis of slew relaxation for low-impact clock buffers.

Scott Lerner, Eric Leggett, Baris Taskin

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS.

Scott Lerner, Baris Taskin

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors.

Scott Lerner, Baris Taskin

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Stability of Rotary Traveling Wave Oscillators under process variations and NBTI.

Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015

Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation.

Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

Timing characterization of clock buffers for clock tree synthesis.

Can Sitik, Scott Lerner, Baris Taskin

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2008

A High-Speed Optical Multi-Drop Bus for Computer Interconnections.

Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals

Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008