Seiji Mochizuki

According to our database, Seiji Mochizuki authored at least 18 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images.

Yusei Horikawa, Seiji Mochizuki, Kousuke Imamura, Tetsuya Matsumura

Proceedings of the IEEE International Conference on Internet of Things and Intelligence Systems, 2023

Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video.

Mai Yamaguchi, Mai Yamakawa, Seiji Mochizuki, Kousuke Imamura, Toshiki Kanamoto, Tetsuya Matsumura

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System.

Yusei Horikawa, Renpei Yoshida, Seiji Mochizuki, Tetsuya Matsumura

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control.

Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei

IEEE J. Solid State Circuits, 2022

2021

4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control.

Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019

Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis.

Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki

Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

2018

Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices.

Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura

Proceedings of the IEEE International Conference on Internet of Things and Intelligence System, 2018

2017

A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.

Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems.

Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

71% Reducing the memory bandwidth requirement for a multi-standard video codec by lossless compression of video using a combination of 2D-DPCM and Variable Length Coding.

Chi Lan Phuong Nguyen, My Phi Ngoc Nguyen, Hung Van Cao, Katsushige Matsubara, Keisuke Matsumoto, Seiji Mochizuki, Kenichi Iwata

Proceedings of the International Conference on IC Design and Technology, 2016

2012

Intra texture prediction based on repetitive pixel replenishment.

Kenichi Iwata, Ryoji Hashimoto, Seiji Mochizuki, Kiyoharu Aizawa

Proceedings of the 19th IEEE International Conference on Image Processing, 2012

2011

A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder.

Tuan Minh Phan Ho, Thang Minh Le, Khanh Duy Vu, Seiji Mochizuki, Kenichi Iwata, Keisuke Matsumoto, Hiroshi Ueda

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits.

Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori

IEEE J. Solid State Circuits, 2010

2009

A Full HD Multistandard Video Codec for Mobile Applications.

Motoki Kimura, Kenichi Iwata, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Hiromi Watanabe

IEEE Micro, 2009

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS.

Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe

IEEE J. Solid State Circuits, 2009

A 342mW mobile application processor with full-HD multi-standard video codec.

Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture.

Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS.

Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe

IEEE J. Solid State Circuits, 2008