Toshihiro Hattori

According to our database1, Toshihiro Hattori authored at least 36 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D.
J. Solid-State Circuits, 2020

2019
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.
IEICE Transactions, 2017

2016
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.
J. Solid-State Circuits, 2015

2013
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.
IEEE Micro, 2013

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
Low-power and high-performance technologies for mobile SoC in LTE era.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.
J. Solid-State Circuits, 2010

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits.
J. Solid-State Circuits, 2010

On coding for nonbinary sources with side information at the decoder.
Proceedings of the International Symposium on Information Theory and its Applications, 2010

2009
An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.
Microprocess. Microsystems, 2009

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU.
J. Solid-State Circuits, 2009

Multi-Core/Multi-IP Technology for Embedded Applications.
IEICE Transactions, 2009

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 342mW mobile application processor with full-HD multi-standard video codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Multicore design is the challenge! what is the solution?
Proceedings of the 45th Design Automation Conference, 2008

2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
J. Solid-State Circuits, 2007

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.
IEICE Transactions, 2007

Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs.
IEEE Design & Test of Computers, 2007

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Development of processor cores for digital consumer appliances.
Systems and Computers in Japan, 2006

SH-X: An embedded processor core for consumer appliances.
J. Embedded Computing, 2006

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.
IEICE Transactions, 2006


2005
SH-X: an embedded processor core for consumer appliances.
SIGARCH Computer Architecture News, 2005

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Transactions, 2005

SH-mobile - low power application processor for cellular [3G cellular phones].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low-Power Design of 90-nm SuperH Processor Core.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2003
Design methodology of low-power microprocessors.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2001
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
Proceedings of ASP-DAC 2001, 2001

1998
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.
Proceedings of the 35th Conference on Design Automation, 1998


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