Toshihiro Hattori
According to our database1,
Toshihiro Hattori
authored at least 43 papers
between 1998 and 2023.
Collaborative distances:
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Bibliography
2023
2021
IEEE Des. Test, 2021
2020
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D.
IEEE J. Solid State Circuits, 2020
2019
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
2016
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.
IEEE J. Solid State Circuits, 2015
2014
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.
IEEE Micro, 2013
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.
IEEE J. Solid State Circuits, 2010
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits.
IEEE J. Solid State Circuits, 2010
Proceedings of the International Symposium on Information Theory and its Applications, 2010
2009
An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.
Microprocess. Microsystems, 2009
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU.
IEEE J. Solid State Circuits, 2009
IEICE Trans. Electron., 2009
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits, 2007
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.
IEICE Trans. Electron., 2007
IEEE Des. Test Comput., 2007
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Syst. Comput. Jpn., 2006
IEICE Trans. Electron., 2006
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006
Hierarchical power distribution and power management scheme for a single chip mobile processor.
Proceedings of the 43rd Design Automation Conference, 2006
2005
SIGARCH Comput. Archit. News, 2005
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Trans. Electron., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2001
Proceedings of ASP-DAC 2001, 2001
1999
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode.
IEEE J. Solid State Circuits, 1999
1998
Proceedings of the 35th Conference on Design Automation, 1998