Toshiki Kanamoto

According to our database, Toshiki Kanamoto authored at least 40 papers between 1999 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Bayesian neural network based inductance calculations of wireless power transfer systems.

Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa

IEICE Electron. Express, 2023

Electronic component placement optimization for heat measures of smartglasses.

Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa

IEICE Electron. Express, 2023

A parabolic spiral coil transmitter with uniform magnetic field for smart devices.

Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa

IEICE Electron. Express, 2023

A thermally optimizing method of thin film resistor trimming with machine learning.

Taisei Arima, Shigeru Hidaka, Ryosuke Watanabe, Tomoya Akasaka, Atsushi Kurokawa, Toshiki Kanamoto

IEICE Electron. Express, 2023

Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video.

Mai Yamaguchi, Mai Yamakawa, Seiji Mochizuki, Kousuke Imamura, Toshiki Kanamoto, Tetsuya Matsumura

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

LoRa Based Wireless Sensor Network for Bus Tracking System in Contoured Castle Town.

Fumiya Sano, Kouki Fukuda, Shinji Kubo, Sumio Tanba, Yamato Ishida, Atushi Kurokawa, Toshiki Kanamoto

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022

A bernoulli spiral coil transmitter for charging various small electronic devices.

Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa

IEICE Electron. Express, 2022

Receiver coil built into belt for heat dissipation of watch-type smart devices.

Shinsuke Kashiwazaki, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa

IEICE Electron. Express, 2022

Enhanced laser trimming of thin film resistors dedicated to snubber for high power IGBT modules.

Ryosuke Watanabe, Shigeru Hidaka, Tomoya Akasaka, Shota Kajiya, Taisei Arima, Atsushi Kurokawa, Toshiki Kanamoto

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems.

Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

A Parabolic Spiral Coil Transmitter for Charging Multiple Receivers.

Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021

Effective methods to promote heat dissipation of wrist wearables.

Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Shinsuke Kashiwazaki, Kyosuke Kusumi, Atsushi Kurokawa

IEICE Electron. Express, 2021

A Virtual Optical Holographic Encryption System Using Expanded Diffie-Hellman Algorithm.

Peng Yang, Tomoyuki Nagase, Toshiki Kanamoto, Tsutomu Zeniya, Shan You

IEEE Access, 2021

2020

Thermal Model and Countermeasures for Future Smart Glasses.

Kodai Matsuhashi, Toshiki Kanamoto, Atsushi Kurokawa

Sensors, 2020

Thermal placement on PCB of components including 3D ICs.

Yuuta Satomi, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa

IEICE Electron. Express, 2020

A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis.

Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai

IEICE Electron. Express, 2020

2019

A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck.

Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Hardware Trojan Insertion and Detection in Asynchronous Circuits.

Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018

Impact of mutual inductance on timing in nano-scale SoC.

Kazuyuki Sakata, Takashi Hasegawa, Kouji Ichikawa, Toshiki Kanamoto

IEICE Electron. Express, 2018

2015

Structure optimization for timing in nano scale FinFET.

Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa

IEICE Electron. Express, 2015

2014

Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate.

Toshiki Kanamoto, Hisato Inaba, Toshiharu Chiba, Yasuhiro Ogasahara

IEICE Electron. Express, 2014

2013

Supply Noise Suppression by Triple-Well Structure.

Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye

IEEE Trans. Very Large Scale Integr. Syst., 2013

2010

Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns.

Kenta Yamada, Toshiyuki Syo, Hisao Yoshimura, Masaru Ito, Tatsuya Kunikiyo, Toshiki Kanamoto, Shigetaka Kumashiro

IEICE Trans. Electron., 2010

A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.

Takashi Sato, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Impact of Self-Heating in Wire Interconnection on Timing.

Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto

IEICE Trans. Electron., 2010

2009

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.

Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.

Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults.

Keiichi Suemitsu, Toshiaki Ito, Toshiki Kanamoto, Masayuki Terai, Satoshi Kotani, Shigeo Sawada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Impact of Well Edge Proximity Effect on Timing.

Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

A Fast Characterizing Method for Large Embedded Memory Modules on SoC.

Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.

Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.

Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation.

Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2005

A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures.

Toshiki Kanamoto, Tetsuya Watanabe, Mitsutoshi Shirota, Masayuki Terai, Tatsuya Kunikiyo, Kiyoshi Ishikawa, Yoshihide Ajioka, Yasutaka Horiba

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004

Efficient capacitance extraction method for interconnects with dummy fills.

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.

Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

1999

The D30V/MPEG multimedia processor.

Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba

IEEE Micro, 1999