Seiya Tanikawa

According to our database1, Seiya Tanikawa authored at least 3 papers between 2013 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2015
Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013


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