Jichoel Bea

According to our database1, Jichoel Bea authored at least 29 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2021
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

2019
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.
Micromachines, 2016

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

New concept of TSV formation methodology using Directed Self-Assembly (DSA).
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

3D memory chip stacking by multi-layer self-assembly technology.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Development of via-last 3D integration technologies using a new temporary adhesive system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration.
Micromachines, 2011

Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Temporary bonding strength control for self-assembly-based 3D integration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Heterogeneous integration technology for MEMS-LSI multi-chip module.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009


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