Shankar Balachandran

According to our database, Shankar Balachandran authored at least 40 papers between 2001 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction.

Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, Onur Mutlu

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021

REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute.

Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute.

Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney

CoRR, 2020

Characterization of Data Generating Neural Network Applications on x86 CPU Architecture.

Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2018

CHOAMP: Cost Based Hardware Optimization for Asymmetric Multicore Processors.

Jyothi Krishna Viswakaran Sreelatha, Shankar Balachandran, Rupesh Nasre

IEEE Trans. Multi Scale Comput. Syst., 2018

Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors.

Jyothi Krishna V. S, Shankar Balachandran

CoRR, 2018

2016

Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers.

Biswabandan Panda, Shankar Balachandran

IEEE Comput. Archit. Lett., 2016

Subclasses of Baxter Permutations Based on Pattern Avoidance.

Shankar Balachandran, Sajin Koroth

Proceedings of the Computer Science - Theory and Applications, 2016

2015

CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores.

Biswabandan Panda, Shankar Balachandran

ACM Trans. Archit. Code Optim., 2015

ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors.

Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti

ACM J. Emerg. Technol. Comput. Syst., 2015

Fast-SL: an efficient algorithm to identify synthetic lethal sets in metabolic networks.

Aditya Pratapa, Shankar Balachandran, Karthik Raman

Bioinform., 2015

A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement.

B. N. Bhramar Ray, Shankar Balachandran

Proceedings of the 28th International Conference on VLSI Design, 2015

Application behavior aware re-reference interval prediction for shared LLC.

Parth Lathigara, Shankar Balachandran, Virendra Singh

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A Soft Error Resilient Low Leakage SRAM Cell Design.

Adithyalal P. M, Shankar Balachandran, Virendra Singh

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

XStat: Statistical <i>X</i>-Filling Algorithm for Peak Capture Power Reduction in Scan Tests.

Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti

J. Low Power Electron., 2014

CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus.

Nihar Rathod, Shankar Balachandran, Neel Gala

Proceedings of the 8th International Workshop on Interconnection Network Architecture, 2014

Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control.

Biswabandan Panda, Shankar Balachandran

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs.

Biswabandan Panda, Shankar Balachandran

Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013

Measuring Area-Complexity Using Boolean Difference.

Ankit Kagliwal, Shankar Balachandran

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

CUPL: a compile-time uncoalesced memory access pattern locator for CUDA.

Madhur Amilkanthwar, Shankar Balachandran

Proceedings of the International Conference on Supercomputing, 2013

LPScan: An algorithm for supply scaling and switching activity minimization during test.

Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

An efficient wirelength model for analytical placement.

B. N. Bhramar Ray, Shankar Balachandran

Proceedings of the Design, Automation and Test in Europe, 2013

TCPT - Thread criticality-driven prefetcher throttling.

Biswabandan Panda, Shankar Balachandran

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012

Set-Cover Heuristics for Two-Level Logic Minimization.

Ankit Kagliwal, Shankar Balachandran

Proceedings of the 25th International Conference on VLSI Design, 2012

CSHARP: Coherence and SHaring Aware Cache Replacement Policies for Parallel Applications.

Biswabandan Panda, Shankar Balachandran

Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency.

Ashok Gautham, Kunal Korgaonkar, Patanjali SLPSK, Shankar Balachandran, Kamakoti Veezhinathan

Proceedings of the 2012 Workshop on Power-Aware Computing Systems, HotPower'12, 2012

Augmentation of Programs with CUDA Streams.

Sharmistha, Madhur Amilkanthwar, Shankar Balachandran

Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Hardware prefetchers for emerging parallel applications.

Biswabandan Panda, Shankar Balachandran

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011.

Nitin Chandrachoodan, Shankar Balachandran

J. Low Power Electron., 2011

A Study on Hierarchical Floorplans of Order k

Shankar Balachandran, Sajin Koroth

CoRR, 2011

A study on the number of Hierarchical Rectangular Partitions of Order k

Shankar Balachandran, Sajin Koroth

CoRR, 2011

A New Wirelength Model for Analytical Placement.

B. N. Bhramar Ray, Shankar Balachandran

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2005

A priori wirelength and interconnect estimation based on circuit characteristic.

Shankar Balachandran, Dinesh Bhatia

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Timing Aware Interconnect Prediction Models for FPGAs.

Shankar Balachandran, Dinesh Bhatia

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

On metrics for comparing interconnect estimation methods for FPGAs.

PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

A-priori wirelength and interconnect estimation based on circuit characteristics.

Shankar Balachandran, Dinesh Bhatia

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002

On Routing Demand and Congestion Estimation for FPGAs.

Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Rapid and Reliable Routability Estimation for FPGAs.

PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia

Proceedings of the Field-Programmable Logic and Applications, 2002

On metrics for comparing routability estimation methods for FPGAs.

PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia

Proceedings of the 39th Design Automation Conference, 2002

2001

fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits.

PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia

Proceedings of the Field-Programmable Logic and Applications, 2001