David Novo

According to our database1, David Novo authored at least 67 papers between 2006 and 2018.

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Bibliography

2018
Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
Design Space Exploration of LDPC Decoders Using High-Level Synthesis.
IEEE Access, 2017

2016
A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures.
CoRR, 2016

Speed and accuracy dilemma in NoC simulation: What about memory impact?
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs.
ACM Trans. Embedded Comput. Syst., 2015

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash.
ACM Trans. Embedded Comput. Syst., 2015

Automatic Application of Power Analysis Countermeasures.
IEEE Trans. Computers, 2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction.
Proceedings of the Hardware and Software: Verification and Testing, 2015

Improved carry chain mapping for the VTR flow.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

A technology mapper for depth-constrained FPGA logic cells.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Automatic support for multi-module parallelism from computational patterns.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Retraining-based timing error mitigation for hardware neural networks.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Constrained interpolation for guided logic synthesis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Hardware system synthesis from Domain-Specific Languages.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Revisiting and-inverter cones.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Wear unleveling: improving NAND flash lifetime by balancing page endurance.
Proceedings of the 12th USENIX conference on File and Storage Technologies, 2014

Energy efficient MIMO processing: A case study of opportunistic run-time approximations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SKETCHILOG: Sketching combinational circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Cracking the complexity of fixed-point refinement in complex wireless systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Making domain-specific hardware synthesis tools cost-efficient.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Shadow And-Inverter Cones.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime.
Proceedings of the Design, Automation and Test in Europe, 2013

An EDA-friendly protection scheme against side-channel attacks.
Proceedings of the Design, Automation and Test in Europe, 2013

Sleuth: Automated Verification of Software Power Analysis Countermeasures.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

Automated circuit elaboration from incomplete architectural descriptions.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Quantization of VLSI digital signal processing systems.
EURASIP J. Adv. Sig. Proc., 2012

Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Selective flexibility: Breaking the rigidity of datapath merging.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Software controlled cell bit-density to improve NAND flash lifetime.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Energy Aware Signal Processing for Software Defined Radio Baseband Implementation.
Signal Processing Systems, 2011

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors.
Signal Processing Systems, 2011

2010
Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Fast performance evaluation of fixed-point systems with un-smooth operators.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Quantization mode opportunities in fixed-point system design.
Proceedings of the 18th European Signal Processing Conference, 2010

Adaptive early-stopping threshold for LTE turbo decoder.
Proceedings of the 18th European Signal Processing Conference, 2010

Exploiting finite precision information to guide data-flow mapping.
Proceedings of the 47th Design Automation Conference, 2010

2009
Energy-performance Exploration of a CGA-based SDR Processor.
Signal Processing Systems, 2009

Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.
IEEE Trans. Signal Processing, 2009

Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Novel energy-efficient scalable soft-output SSFE MIMO detector architectures.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

A System Level Algorithmic Approach toward Energy-Aware SDR Baseband Implementations.
Proceedings of IEEE International Conference on Communications, 2009

Finite precision processing in wireless applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Application-driven adaptive fixed-point refinement for SDRs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures.
Proceedings of IEEE International Conference on Communications, 2008

Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler.
Proceedings of the IEEE International Conference on Acoustics, 2008

Adaptive SSFE Near-ML MIMO Detector with Dynamic Search Range and 80-103Mbps Flexible Implementation.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios.
Proceedings of the Design, Automation and Test in Europe, 2008

Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio.
Proceedings of the Design, Automation and Test in Europe, 2008

How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.
Proceedings of the 45th Design Automation Conference, 2008

2007
A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.
Proceedings of the Embedded Computer Systems: Architectures, 2007

2006
Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A Scalable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio.
Proceedings of the 1st International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2006


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