V. R. Devanathan

According to our database, V. R. Devanathan authored at least 26 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath.

V. R. Devanathan, Sumant Kale

Proceedings of the 2016 IEEE International Test Conference, 2016

2015

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications.

Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti

J. Low Power Electron., 2015

ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors.

Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti

ACM J. Emerg. Technol. Comput. Syst., 2015

Framework for Selective Flip-Flop Replacement for Soft Error Mitigation.

Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti

Proceedings of the 28th International Conference on VLSI Design, 2015

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation.

V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs.

Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions.

Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti

J. Low Power Electron., 2013

Towards adaptive test of multi-core RF SoCs.

Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs.

Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti

J. Low Power Electron., 2012

2011

Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test.

V. R. Devanathan, Ishaan Santhosh Shah

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Techniques to improve memory interface test quality for complex SoCs.

V. R. Devanathan, Srinivas Kumar Vooka

Proceedings of the 2011 IEEE International Test Conference, 2011

Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs.

V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

EOMP: an exactly once multicast protocol for distributed mobile systems.

M. A. Maluk Mohamed, V. R. Devanathan, D. Janakiram

Int. J. Parallel Emergent Distributed Syst., 2010

Towards effective and compression-friendly test of memory interface logic.

V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar

Proceedings of the 2011 IEEE International Test Conference, 2010

2008

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.

V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti

J. Low Power Electron., 2008

2007

Variation-Tolerant, Power-Safe Pattern Generation.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

IEEE Des. Test Comput., 2007

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.

V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti

Proceedings of the 2007 IEEE International Test Conference, 2007

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 2007 IEEE International Test Conference, 2007

Methodology for low power test pattern generation using activity threshold control logic.

Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

J. Low Power Electron., 2006

2005

A Framework for Distributed and Hierarchical Design-for-Test.

C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.

V. R. Devanathan

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2003

A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems.

D. Janaki Ram, M. A. Maluk Mohamed, V. R. Devanathan

Proceedings of the 23rd International Conference on Distributed Computing Systems Workshops (ICDCS 2003 Workshops), 2003