Mirjana Stojilovic

According to our database, Mirjana Stojilovic authored at least 35 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care Hardware Trojans to Shared Cloud FPGAs.

Dina G. Mahmoud, Beatrice Shokry, Vincent Lenders, Wei Hu, Mirjana Stojilovic

IEEE Access, 2024

2023

A Visionary Look at the Security of Reconfigurable Cloud Computing.

Mirjana Stojilovic, Kasper Rasmussen, Francesco Regazzoni, Mehdi B. Tahoori, Russell Tessier

Proc. IEEE, December, 2023

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs.

Ognjen Glamocanin, Shashwat Shrivastava, Jinwei Yao, Nour Ardo, Mathias Payer, Mirjana Stojilovic

J. Hardw. Syst. Secur., September, 2023

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks.

David Spielmann, Ognjen Glamocanin, Mirjana Stojilovic

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

The Side-channel Metrics Cheat Sheet.

Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic

ACM Comput. Surv., 2023

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era.

Dina G. Mahmoud, Vincent Lenders, Mirjana Stojilovic

ACM Comput. Surv., 2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck.

Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors.

Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.

Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Active Wire Fences for Multitenant FPGAs.

Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs.

Ognjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

The Side-Channel Metric Cheat Sheet.

Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic

IACR Cryptol. ePrint Arch., 2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks.

Dina G. Mahmoud, David Dervishi, Samah Hussein, Vincent Lenders, Mirjana Stojilovic

IEEE Access, 2022

FPGA-to-CPU Undervolting Attacks.

Dina G. Mahmoud, Samah Hussein, Vincent Lenders, Mirjana Stojilovic

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time.

Hedi Fendri, Marco Macchetti, Jérôme Perrine, Mirjana Stojilovic

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing.

Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic

IEEE Access, 2021

Deep Learning Detection of GPS Spoofing.

Olivia Jullian, Beatriz Otero, Mirjana Stojilovic, Juan José Costa, Javier Verdú, Manuel Alejandro Pajuelo

Proceedings of the Machine Learning, Optimization, and Data Science, 2021

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs.

Morten B. Petersen, Stefan Nikolic, Mirjana Stojilovic

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks.

Ognjen Glamocanin, Dina G. Mahmoud, Francesco Regazzoni, Mirjana Stojilovic

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs.

Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic

IACR Cryptol. ePrint Arch., 2020

CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors.

Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic

IACR Cryptol. ePrint Arch., 2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer.

Frédéric Gessler, Philip Brisk, Mirjana Stojilovic

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs.

Dina G. Mahmoud, Wei Hu, Mirjana Stojilovic

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Closing Leaks: Routing Against Crosstalk Side-Channel Attacks.

Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs.

Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

FPGA-Assisted Deterministic Routing for FPGAs.

Dario Korolija, Mirjana Stojilovic

Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

A Machine Learning Approach for Power Gating the FPGA Routing Network.

Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic

Proceedings of the International Conference on Field-Programmable Technology, 2019

Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey.

Seyedeh Sharareh Mirzargar, Mirjana Stojilovic

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform.

Dario Korolija, Mirjana Stojilovic

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Timing Violation Induced Faults in Multi-Tenant FPGAs.

Dina Mahmoud, Mirjana Stojilovic

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model.

Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Parallel FPGA routing: Survey and challenges.

Mirjana Stojilovic

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2013

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays.

Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012

Selective flexibility: Breaking the rigidity of datapath merging.

Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012