Shibaji Banerjee

According to our database, Shibaji Banerjee authored at least 11 papers between 2005 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization.

Shibaji Banerjee, Jimson Mathew

J. Low Power Electron., 2017

2013

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.

Jimson Mathew, Saraju P. Mohanty, Shibaji Banerjee, Dhiraj K. Pradhan, Abusaleh M. Jabir

Comput. Electr. Eng., 2013

2011

A Routing-Aware ILS Design Technique.

Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.

Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski

J. Low Power Electron., 2011

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.

Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2007

An Efficient Scan Tree Design for Compact Test Pattern Set.

Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

An integrated DFT solution for mixed-signal SOCs.

Shibaji Banerjee, Debdeep Mukhopadhyay, C. V. G. Rao, Dipanwita Roy Chowdhury

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Built-In Self-Test for Flash Memory Embedded in SoC.

Shibaji Banerjee, Dipanwita Roy Chowdhury

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

Computer Aided Test (CAT) Tool for Mixed Signal SOCs.

Shibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A programmable built-in self-test for embedded DRAMs.

Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

CryptoScan: A Secured Scan Chain Architecture.

Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005