Shin'ichi Wakabayashi

IPSJ Trans. Syst. LSI Des. Methodol., 2023

2022

Introduction of a New Method for Preventing Recipient Unapproved Transactions to Bitcoin Wallet.

[BibT_eX]

[DOI]

Chuki Hayama

Proceedings of the 46th IEEE Annual Computers, Software, and Applications Conferenc, 2022

2021

A Protocol for Preventing Transaction Commitment Without Recipient's Authorization on Blockchain and It's Implementation.

[BibT_eX]

[DOI]

Ryousuke Yamauchi

IEEE Access, 2021

2020

A Verifiable Secret Sharing Scheme without Using Multi-Party Computations.

[BibT_eX]

[DOI]

Takumi Makino

Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020

A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid Clouds.

[BibT_eX]

[DOI]

Shun Kawamoto

Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020

2019

A Protocol for Preventing Transaction Commitment without Recipient's Authorization on Blockchain.

[BibT_eX]

[DOI]

Ryosuke Yamauchi

Proceedings of the 43rd IEEE Annual Computer Software and Applications Conference, 2019

2018

A Nearest Neighbor Search Engine Using Distance-Based Hashing.

[BibT_eX]

[DOI]

Toshitaka Ito

Yuri Itotani

Proceedings of the International Conference on Field-Programmable Technology, 2018

Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection.

[BibT_eX]

[DOI]

Gaku Kataoka

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing.

[BibT_eX]

[DOI]

Yuri Itotani

Proceedings of the Database and Expert Systems Applications, 2018

2016

An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data.

[BibT_eX]

[DOI]

Yuto Arai

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.

[BibT_eX]

[DOI]

Yuichi Nakamura

Yasuhiro Takashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014

An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2014

An ILP-Based Optimal Circuit Mapping Method for PLDs.

[BibT_eX]

[DOI]

Hiroki Nishiyama

Keisuke Inoue

Mineo Kaneko

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013

A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions.

[BibT_eX]

[DOI]

Yasuhiro Shintani

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2011

An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations.

[BibT_eX]

[DOI]

Satoru Nakano

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

An FPGA-based text search engine for approximate regular expression matching.

[BibT_eX]

[DOI]

Yuichiro Utan

Proceedings of the International Conference on Field-Programmable Technology, 2010

2009

A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set.

[BibT_eX]

Yosuke Kawanaka

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008

A systolic regular expression pattern matching engine and its application to network intrusion detection.

[BibT_eX]

[DOI]

Yosuke Kawanaka

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007

A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning.

[BibT_eX]

Takayoshi Shimazu

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation.

[BibT_eX]

[DOI]

Yoshihiro Kimura

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006

A Decision Method of Attribute Importance for Classification by Outlier Detection.

[BibT_eX]

[DOI]

Tomotake Nakamura

Proceedings of the 22nd International Conference on Data Engineering Workshops, 2006

FPGA implementation of tabu search for the quadratic assignment problem.

[BibT_eX]

[DOI]

Yoshihiro Kimura

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

A Clustering Method Using an Irregular Size Cell Graph.

[BibT_eX]

[DOI]

Tomotake Nakamura

Proceedings of the 15th International Workshop on Research Issues in Data Engineering (RIDE-SDMA 2005), 2005

Feature Extraction of Clusters Based on FlexDice.

[BibT_eX]

[DOI]

Tomotake Nakamura

Proceedings of the 21st International Conference on Data Engineering Workshops, 2005

An Algorithm for Computing Global-Based Outlier Degrees on Data Sets.

[BibT_eX]

[DOI]

Takeshi Fushimi

Proceedings of the 21st International Conference on Data Engineering Workshops, 2005

Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs.

[BibT_eX]

Kenji Kikuchi

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004

An Instance-Specific Hardware Algorithm for Finding a Maximum Clique.

[BibT_eX]

[DOI]

Kenji Kikuchi

Proceedings of the Field Programmable Logic and Application, 2004

2002

A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time.

[BibT_eX]

[DOI]

Shigeki Takekawa

Syst. Comput. Jpn., 2002

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation.

[BibT_eX]

[DOI]

Shinya Yamasaki

Shingo Nakaya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem.

[BibT_eX]

[DOI]

Algorithmica, 2002

A hierarchical standard cell placement method based on a new cluster placement model.

[BibT_eX]

[DOI]

Nobuyuki Iwauchi

Hajime Kubota

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual.

[BibT_eX]

[DOI]

Koichi Hatta

Syst. Comput. Jpn., 2001

2000

An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair.

[BibT_eX]

[DOI]

Shingo Nakaya

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Genetic algorithm accelerator GAA-II.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer.

[BibT_eX]

[DOI]

Takahiro Deguchi

Proceedings of ASP-DAC 2000, 2000

1999

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout.

[BibT_eX]

[DOI]

Integr., 1999

An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair.

[BibT_eX]

[DOI]

Koichi Hatta

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm.

[BibT_eX]

[DOI]

Koichi Hatta

Masashige Suzuki

Proceedings of the Parallel Problem Solving from Nature, 1998

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

1997

A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs.

[BibT_eX]

[DOI]

Mitsuhiro Ono

Yutaka Nishimaru

Integr., 1997

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs.

[BibT_eX]

[DOI]

Mitsuhiro Ono

Yutaka Nishimaru

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Pin assignment with global routing for VLSI building block layout.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A three-layer over-the-cell multi-channel router for a new cell model.

[BibT_eX]

[DOI]

Masahiro Tsuchiya

Integr., 1996

1995

A Verification Algorithm for Logic Circuits with Internal Variables.

[BibT_eX]

[DOI]

Toshihiro Nakaoa

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An MCM Routing Algorithm Considering Crosstalk.

[BibT_eX]

[DOI]

Tetsuya Miyoshi

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A three-layer over-cell multi-channel routing method for a new cell model.

[BibT_eX]

[DOI]

Masahiro Tsuchiya

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A new performance driven placement method with the Elmore delay model for row based VLSIs.

[BibT_eX]

[DOI]

Mitsuhiro Ono

Yutaka Nishimaru

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A new system partitioning method under performance and physical constraints for multi-chip modules.

[BibT_eX]

[DOI]

Yoshinori Katsura

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

A Systolic Graph Partitioning Algorithm for VLSI Design.

[BibT_eX]

[DOI]

Kazunori Isomoto

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Floorplanning Method with Topological Constraint Manipulation.

[BibT_eX]

[DOI]

Yoshinori Katsura

Katsumi Yamatani

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

On Three-Way Graph Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A new global routing algorithm for over-the-cell routing in standard cell layouts.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

1992

An optimal channel pin assignment with multiple intervals for building block layout.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

1989

Visualized and modeless programming environment for form manipulation language.

[BibT_eX]

[DOI]

Jun'ichi Miyao

Yasushi Ohtahara

Proceedings of the IEEE Workshop on Visual Languages, 1989

1985

Design of hardware algorithms by recurrence relations.

[BibT_eX]

[DOI]

Tohru Kikuno