Keisuke Inoue
According to our database1,
Keisuke Inoue
authored at least 42 papers
between 1991 and 2020.
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Bibliography
2020
Proceedings of the 15th International Joint Conference on Computer Vision, 2020
2019
An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
2018
Proceedings of the Advances on Broadband and Wireless Computing, 2018
2017
A dependable ASIC architecture with RT-level rollback for controller soft error recovery.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the Frontiers in Algorithmics - 8th International Workshop, 2014
2013
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
2012
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Early planning for RT-level delay insertion during clock skew-aware register binding.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Ordered coloring-based resource binding for datapaths with improved skew-adjustability.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Discourse analysis of online chat reference interviews for modeling online information-seeking dialogues.
Proceedings of the Thriving on Diversity: Information Opportunities in a Pluralistic World, 2009
2008
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the 26th International Conference on Computer Design, 2008
2006
Proceedings of the Open Source Systems, 2006
2005
Knowledge Discovery from Heterogeneous Dynamic Systems using Change-Point Correlations.
Proceedings of the 2005 SIAM International Conference on Data Mining, 2005
2003
J. Robotics Mechatronics, 2003
2001
IEEE J. Solid State Circuits, 2001
Comput. Aided Des., 2001
2000
Proceedings of the 9th International Meshing Roundtable, 2000
1999
Proceedings of the 8th International Meshing Roundtable, 1999
ISIS: Multiprocessor Simulator Library.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999
1998
Automated Conversion of 2D Triangular Mesh into Quadrilateral Mesh with Directionality Control.
Proceedings of the 7th International Meshing Roundtable, 1998
1997
Syst. Comput. Jpn., 1997
Traffic Control Model with Neural Network Analogy.
Proceedings of the Progress in Connectionist-Based Information Systems: Proceedings of the 1997 International Conference on Neural Information Processing and Intelligent Information Systems, 1997
Proceedings of the Euro-Par '97 Parallel Processing, 1997
1996
Proceedings of the Field-Programmable Logic, 1996
1991
Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991