Yuichi Nakamura

Hitoshi Takeshita

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2021

Can Quantum Technologies Change "Consumer Electronics"?

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2021

Theoretical and Experimental Analysis of Traveling Salesman Walk Problem.

[BibT_eX]

[DOI]

Emmanuel Le Taillandier de Gabory

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2019

Past, Current and Future Technologies for Optical Submarine Cables.

[BibT_eX]

[DOI]

Hitoshi Takeshita

Masaki Sato

Yoshihisa Inada

Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019

2018

Silicon Photonics for Computing Systems.

[BibT_eX]

[DOI]

Jiang Xu

Andrew B. Kahng

ACM J. Emerg. Technol. Comput. Syst., 2018

Task Allocation and Scheduling Optimization in the Heterogeneous Core System.

[BibT_eX]

[DOI]

Proceedings of the 2018 New Generation of CAS, 2018

2017

A Loitering Discovery System Using Efficient Similarity Search Based on Similarity Hierarchy.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 2.

[BibT_eX]

[DOI]

Linghe Kong

Kui Ren

Muhammad Khurram Khan

IEEE Commun. Mag., 2017

Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 1.

[BibT_eX]

[DOI]

Linghe Kong

Kui Ren

Muhammad Khurram Khan

IEEE Commun. Mag., 2017

The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Novel heterogeneous computing platforms and 5G communications for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Accelerating NFV application using CPU-FPGA tightly coupled architecture.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

Future trend of deep learning frameworks - From the perspective of big data analytics and HPC.

[BibT_eX]

[DOI]

Takuya Araki

Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2016

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

PEVaS: Power and execution-time variation-aware scheduling for MPSoC.

[BibT_eX]

[DOI]

Komei Nomura

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.

[BibT_eX]

[DOI]

Masato Inagi

Shin'ichi Wakabayashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

FPGA-accelerated complex event processing.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

2014

An NoC-based evaluation platform for safety-critical automotive applications.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis.

[BibT_eX]

[DOI]

Naoya Okada

Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Revisiting rendezvous protocols in the context of RDMA-capable host channel adapters and many-core processors.

[BibT_eX]

[DOI]

Proceedings of the 20th European MPI Users's Group Meeting, 2013

Adaptive sensing of ECG signals using R-R interval prediction.

[BibT_eX]

[DOI]

Shogo Nakaya

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012

A non-volatile reconfigurable offloader for wireless sensor nodes.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2012

An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip.

[BibT_eX]

[DOI]

Hiroshi Saito

Tomohiro Yoneda

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

2011

A Verification and Analysis Tool Set for Embedded System Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology.

[BibT_eX]

[DOI]

Proceedings of the HOST 2011, 2011

A low power technology mapping method for Adaptive Logic Module.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.

[BibT_eX]

[DOI]

Masato Inagi

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Delay analysis of sub-path on fabricated chips by several path-delay tests.

[BibT_eX]

[DOI]

Takanobu Shiki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.

[BibT_eX]

[DOI]

Masato Inagi

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools.

[BibT_eX]

[DOI]

Katsunori Tanaka

Atsushi Atarashi

IPSJ Trans. Syst. LSI Des. Methodol., 2008

A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2008

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Post-Silicon Clock-Timing Tuning Based on Statistical Estimation.

[BibT_eX]

[DOI]

Yuko Hashizume

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fine-Grained Power Gating Based on the Controlling Value of Logic Elements.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A design method for skew tolerant latch design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A Relocation Method for Circuit Modifications.

[BibT_eX]

[DOI]

Kunihiko Yanagibashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs.

[BibT_eX]

[DOI]

Kohei Hosokawa

Katsunori Tanaka

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

Domino Logic Synthesis System and its Applications.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2006

Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Fast FPGA-Emulation-Based Simulation Environment for Custom Processors.

[BibT_eX]

[DOI]

Kohei Hosokawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Budgeting-free hierarchical design method for large scale and high-performance LSIs.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs.

[BibT_eX]

[DOI]

Ko Yoshikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Timing optimization by replacing flip-flops to latches.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

1997

A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface.

[BibT_eX]

[DOI]

Yoshiyuki Ito

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995

Multi-Level Logic Minimization Based on Multi-Signal Implications.

[BibT_eX]

[DOI]

Masayuki Yuguchi

Kazutoshi Wakabayashi

Tomoyuki Fujita

Proceedings of the 32st Conference on Design Automation, 1995

A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix.

[BibT_eX]

[DOI]