Sounil Biswas

According to our database, Sounil Biswas authored at least 13 papers between 2003 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A Low-Power, Low-Noise, High-Performance Re-Convergent Clock Mesh Design for Large AI Compute Clusters.

Harivinay Kancharla, Sounil Biswas

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2016

SERDES external loopback test using production parametric-test hardware.

Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi

Proceedings of the 2016 IEEE International Test Conference, 2016

2014

Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis.

Sounil Biswas, Hongfei Wang, R. D. (Shawn) Blanton

ACM Trans. Design Autom. Electr. Syst., 2014

Innovative practices session 5C: Machine learning and data analysis in test.

Sounil Biswas, John M. Carulli, Dragoljub Gagi Drmanac, Arpan Bhattacherjee

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2012

An Industrial Study of System-Level Test.

Sounil Biswas, Bruce Cory

IEEE Des. Test Comput., 2012

2011

Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data.

Sounil Biswas, Ronald D. Blanton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2009

Maintaining Accuracy of Test Compaction through Adaptive Re-learning.

Sounil Biswas, Ronald D. Blanton

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008

Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.

Sounil Biswas, R. D. (Shawn) Blanton

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Improving the Accuracy of Test Compaction through Adaptive Test Update.

Sounil Biswas, Ronald D. Blanton

Proceedings of the 2008 IEEE International Test Conference, 2008

2006

Statistical Test Compaction Using Binary Decision Trees.

Sounil Biswas, Ronald D. Blanton

IEEE Des. Test Comput., 2006

2005

Specification Test Compaction for Analog Circuits and MEMS.

Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi

Proceedings of the 2005 Design, 2005

2004

Generalized Sensitization using Fault Tuples.

Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2003

A Path Sensitization Technique for Testing of Switched Capacitor Circuits.

Sounil Biswas, Baquer Mazhari

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003