Stefan Pechmann

Orcid: 0000-0001-6890-3378

According to our database1, Stefan Pechmann authored at least 9 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Current Mirror Based Read Circuit Design with Multi-Level Capability for Resistive Switching Devices.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

A High-speed Low-power Sense Amplifier for the RRAM Array with Multi-level Reading Function using 130-nm Technology.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

2020
A Parallel-friendly Majority Gate to Accelerate In-memory Computation.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020


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