Johannes Knödtel

According to our database, Johannes Knödtel authored at least 12 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Trusted Computing Architectures for IoT Devices.

An Braeken, Bruno da Silva, Laurent Segers, Johannes Knödtel, Marc Reichenbach, Cornelia Wulf, Sergio A. Pertuz, Diana Göhringer, Jo Vliegen, Md Masoom Rabbani, Nele Mentens

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration.

Johannes Knödtel, Marc Reichenbach

Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023

TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs.

Johannes Knödtel, Hector Gerardo Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Marc Reichenbach

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2022

Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?

Johannes Knödtel, Sebastian Rachuj, Marc Reichenbach

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems.

Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey

IEEE Access, 2021

Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks.

Markus Fritscher, Johannes Knödtel, Maen Mallah, Stefan Pechmann, Emilio Pérez-Bosch Quesada, Tommaso Rizzi, Christian Wenger, Marc Reichenbach

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations.

Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

2020

A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories.

Johannes Knödtel, Markus Fritscher, Daniel Reiser, Dietmar Fey, Marco Breiling, Marc Reichenbach

Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019

Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools.

Markus Fritscher, Johannes Knödtel, Marc Reichenbach, Dietmar Fey

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

A programmable ternary CPU using hybrid CMOS/memristor circuits.

Daniel Wust, Dietmar Fey, Johannes Knödtel

Int. J. Parallel Emergent Distributed Syst., 2018

A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs.

Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2017

Prototyping memristors in digital system with an FPGA-based testing environment.

Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach, Christopher Söll, Dietmar Fey

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017