Yves Mathieu

According to our database, Yves Mathieu authored at least 35 papers between 1988 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Jitter Compensation Mechanism for Dynamic Deterministic Networks.

Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2021

Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.

Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma

IEEE Trans. Inf. Forensics Secur., 2021

Formal Evaluation and Construction of Glitch-resistant Masked Functions.

Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

2020

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.

Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

IEEE Trans. Computers, 2020

2019

Cache-Timing Attacks Still Threaten IoT Devices.

Sofiane Takarabt, Alexander Schaub, Adrien Facon, Sylvain Guilley, Laurent Sauvage, Youssef Souissi, Yves Mathieu

Proceedings of the Codes, Cryptology and Information Security, 2019

2018

Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification.

Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology.

Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

Cryptographically Secure Shield for Security IPs Protection.

Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin

IEEE Trans. Computers, 2017

2016

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology.

Sumanta Chaudhuri, Tarik Graba, Yves Mathieu

CoRR, 2016

2015

Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA.

Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

Cryptographically secure shields.

Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, David Naccache, Xuan Thuy Ngo

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security.

Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.

Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata

Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014

2013

Design methodology of an ASIC TRNG based on an open-loop delay chain.

Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger, Yves Mathieu

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA.

Zouha Cherif, Jean-Luc Danger, Florent Lozach, Yves Mathieu, Lilian Bossuet

Proceedings of the HASP 2013, 2013

Graphics Composition for Multiview Displays.

Jean Le Feuvre, Yves Mathieu

Proceedings of the Emerging Technologies for 3D Video: Creation, 2013

2012

Exploration of 3D grid caching strategies for ray-shooting.

Stéphane Mancini, Zahir Larabi, Yves Mathieu, Tomasz Toczek, Lionel Pierrefeu

J. Real Time Image Process., 2012

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography.

Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu

Int. J. Reconfigurable Comput., 2012

A dual threshold voltage technique for glitch minimization.

Mariem Slimani, Philippe Matherat, Yves Mathieu

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2010

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics.

Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu

Int. J. Reconfigurable Comput., 2010

Cross-Correlation Cartography.

Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Calibrating a predictive cache emulator for SoC design.

Stéphane Mancini, Lionel Pierrefeu, Zahir Larabi, Yves Mathieu

Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Balancing exploration and exploitation in an adaptive three-dimensional cellular genetic algorithm via a probabilistic selection operator.

Asmaa Al-Naqi, Ahmet T. Erdogan, Tughrul Arslan, Yves Mathieu

Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009

Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.

Laurent Sauvage, Sylvain Guilley, Yves Mathieu

ACM Trans. Reconfigurable Technol. Syst., 2009

Efficient Data Access Management for FPGA-Based Image Processing SoCs.

Zahir Larabi, Yves Mathieu, Stéphane Mancini

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

DPL on Stratix II FPGA: What to Expect?.

Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.

Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

High Efficiency Reconfigurable Cache for Image Processing.

Zahir Larabi, Yves Mathieu, Stéphane Mancini

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.

Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.

Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu

Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008

2007

Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.

Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu

IEEE Des. Test Comput., 2007

2005

The "Backend Duplication" Method.

Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004

CMOS Structures Suitable for Secured Hardware.

Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost

Proceedings of the 2004 Design, 2004

2003

A coprocessor for real-time MPEG4 facial animation on mobiles.

Christophe Cunat, Jean Gobert, Yves Mathieu

Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

1988

Architectures for Mass Market 3D Displays.

Paul Winser, Thierry Bonnet, Dominique Dumont, Yves Mathieu

Proceedings of the 9th European Computer Graphics Conference and Exhibition, 1988