Gerald Hempel

Orcid: 0000-0002-4737-8612

According to our database1, Gerald Hempel authored at least 14 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

2022
Brain-inspired Cognition in Next-generation Racetrack Memories.
ACM Trans. Embed. Comput. Syst., November, 2022

2021
Mocasin - Rapid Prototyping of Rapid Prototyping Tools: A Framework for Exploring New Approaches in Mapping Software to Heterogeneous Multi-cores.
Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021

From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

2019
Generation of Application Specific Hardware Extensions for Hybrid Architectures: The Development of PIRANHA - A GCC Plugin for High-Level-Synthesis.
PhD thesis, 2019

2017
Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

2015
GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs.
CoRR, 2015

An architectural template for composing application specific datapaths at runtime.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

2012
Towards GCC-based automatic soft-core customization.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2010
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2007
A resource optimized SoC Kit for FPGAs.
Proceedings of the FPL 2007, 2007

A resource optimized Processor Core for FPGA based SoCs.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007


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