Asif Ali Khan

João Paulo C. de Lima

Hamid Farzaneh

CoRR, 2024

Full-Stack Optimization for CAM-Only DNN Inference.

[BibT_eX]

[DOI]

João Paulo C. de Lima

Luigi Carro

João Paulo Cardoso de Lima

CoRR, 2024

2023

DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, September, 2023

ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees.

[BibT_eX]

[DOI]

IEEE Trans. Computers, May, 2023

C4CAM: A Compiler for CAM-based In-memory Accelerators.

[BibT_eX]

[DOI]

Hamid Farzaneh

CoRR, 2023

CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms.

[BibT_eX]

[DOI]

CoRR, 2023

Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.

[BibT_eX]

[DOI]

João Paulo C. de Lima

Proceedings of the International Conference on Compilers, 2023

Investigation of Cloud Forensic Incidents in Cloud Architecture for 6G Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2023

2022

Brain-inspired Cognition in Next-generation Racetrack Memories.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., November, 2022

Design and Code Optimization for Systems with Next-generation Racetrack Memories.

[BibT_eX]

[DOI]

PhD thesis, 2022

ALPHA: A Novel Algorithm-Hardware Co-Design for Accelerating DNA Seed Location Filtering.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

DNA Pre-Alignment Filter Using Processing Near Racetrack Memory.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2022

HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches.

[BibT_eX]

[DOI]

Proceedings of the DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17, 2022

2021

Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2020

Polyhedral Compilation for Racetrack Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade.

[BibT_eX]

[DOI]

Robin Bläsing

Panagiotis Ch. Filippou

Proc. IEEE, 2020

Generalized Data Placement Strategies for Racetrack Memories.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

RTSim: A Cycle-Accurate Simulator for Racetrack Memories.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

Performance and Energy-Efficient Design of STT-RAM Last-Level Cache.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

NVMain Extension for Multi-Level Cache Systems.

[BibT_eX]

[DOI]