Jerónimo Castrillón

According to our database1, Jerónimo Castrillón authored at least 57 papers between 2005 and 2019.

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Bibliography

2019
Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient Computing.
Proceedings of the IEEE, 2019

RTSim: A Cycle-Accurate Simulator for Racetrack Memories.
Computer Architecture Letters, 2019

TeIL: a type-safe imperative tensor intermediate language.
Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, 2019

Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads.
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

2018
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache.
IEEE Trans. VLSI Syst., 2018

A Domain-Specific Language and Editor for Parallel Particle Methods.
ACM Trans. Math. Softw., 2018

A Hardware/Software Stack for Heterogeneous Systems.
IEEE Trans. Multi-Scale Computing Systems, 2018

NVMain Extension for Multi-Level Cache Systems.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

Supporting Fine-grained Dataflow Parallelism in Big Data Systems.
Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores, 2018

On the Representation of Mappings to Multicores.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

Meta-programming for cross-domain tensor optimizations.
Proceedings of the 17th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences, 2018

CFDlang: High-level code generation for high-order methods in fluid dynamics.
Proceedings of the Real World Domain Specific Languages Workshop, 2018

Compiling for concise code and efficient I/O.
Proceedings of the 27th International Conference on Compiler Construction, 2018

2017
MAPS: A Software Development Environment for Embedded Multicore Applications.
Handbook of Hardware/Software Codesign, 2017

Symmetry in Software Synthesis.
TACO, 2017

Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061).
Dagstuhl Reports, 2017

Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

System simulation with gem5 and SystemC: The keystone for full interoperability.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Analyzing State-of-the-Art Role-based Programming Languages.
Proceedings of the Companion to the first International Conference on the Art, 2017

Efficient STT-RAM last-level-cache architecture to replace DRAM cache.
Proceedings of the International Symposium on Memory Systems, 2017

Application interference analysis: Towards energy-efficient workload management on heterogeneous micro-server architectures.
Proceedings of the 2017 IEEE Conference on Computer Communications Workshops, 2017

Architecture, Languages, Compilation and Hardware support for Emerging ManYcore systems (ALCHEMY): Preface.
Proceedings of the International Conference on Computational Science, 2017

Towards compositional and generative tensor optimizations.
Proceedings of the 16th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences, 2017

Rethinking on-chip DRAM cache for simultaneous performance and energy optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Trading Fault Tolerance for Performance in AN Encoding.
Proceedings of the Computing Frontiers Conference, 2017

Multi-grained performance estimation for MPSoC compilers: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

Extending a Compiler Backend for Complete Memory Error Detection.
Proceedings of the Automotive - Safety & Security 2017, 2017

2016
Guest Editorial: Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES).
ACM Trans. Embedded Comput. Syst., 2016

An optimal allocation of memory buffers for complex multicore platforms.
Journal of Systems Architecture - Embedded Systems Design, 2016

Compile- and run-time approaches for the selection of efficient data structures for dynamic graph analysis.
Applied Network Science, 2016

High-level NoC model for MPSoC compilers.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case Study.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Fault tolerance with aspects: a feasibility study.
Proceedings of the 15th International Conference on Modularity, 2016

2015
Efficient Data Structures for Dynamic Graph Analysis.
Proceedings of the 11th International Conference on Signal-Image Technology & Internet-Based Systems, 2015

ViPES 2015 - Preface.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Compiling for Resilience: the Performance Gap.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015

Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Multi/many-core programming: where are we standing?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Automatic detection of concurrency bugs through event ordering constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Software Compilation Techniques for MPSoCs.
Proceedings of the Handbook of Signal Processing Systems, 2013

Programming heterogeneous MPSoCs: tool flows to close the software productivity gap.
PhD thesis, 2013

MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs.
IEEE Trans. Industrial Informatics, 2013

Efficient Implementation of Application-Aware Spinlock Control in MPSoCs.
IJERTCS, 2013

Split-cost communication model for improved MPSoC application mapping.
Proceedings of the 2013 International Symposium on System on Chip, 2013

2012
Application-aware spinlock control using a hardware scheduler in MPSoC platforms.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Communication-aware mapping of KPN applications onto heterogeneous MPSoCs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.
IJERTCS, 2011

Trends in embedded software synthesis.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

2010
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms.
Proceedings of the Design, Automation and Test in Europe, 2010

MPSoC programming using the MAPS compiler.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Software Compilation Techniques for MPSoCs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Task management in MPSoCs: An ASIP approach.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A high-level virtual platform for early MPSoC software development.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
MAPS: an integrated framework for MPSoC application parallelization.
Proceedings of the 45th Design Automation Conference, 2008

2005
Reinforcement Learning with Kohonen-based State Aggregation for Obstacle Avoidance of a Mobile Robot.
Proceedings of the Memorias del Congreso Internacional de Inteligencia Computacional, 2005


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