Sudheer K. Vemulapalli

Affiliations:
  • Texas Instruments Inc., Dallas, TX, USA


According to our database1, Sudheer K. Vemulapalli authored at least 8 papers between 1995 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2011
Spur-free all-digital PLL in 65nm for mobile phones.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 0.8mm<sup>2</sup> all-digital SAW-less polar transmitter in 65nm EDGE SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

2006
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process.
IEEE J. Solid State Circuits, 2006

2005
All-digital PLL and transmitter for mobile phones.
IEEE J. Solid State Circuits, 2005


1995
Dual-Crosshatch Disk Array: A Highly Reliable Hybrid-RAID Architecture.
Proceedings of the 1995 International Conference on Parallel Processing, 1995


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