Gennady Feygin

According to our database1, Gennady Feygin authored at least 15 papers between 1991 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Relaxed Polar Codes.
IEEE Trans. Inf. Theory, 2017

2015
Relaxed channel polarization for reduced complexity polar coding.
Proceedings of the 2015 IEEE Wireless Communications and Networking Conference, 2015

2010
A 0.8mm<sup>2</sup> all-digital SAW-less polar transmitter in 65nm EDGE SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

2006
LMS-based calibration of an RF digitally controlled oscillator for mobile phones.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

2001
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1997
A 160-MHz analog equalizer for magnetic disk read Channel.
IEEE J. Solid State Circuits, 1997

1996
RACER: a reconfigurable constraint-length 14 Viterbi decoder.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1994
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
Inf. Process. Manag., 1994

Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.
Proceedings of the IEEE Data Compression Conference, 1994

1993
A multiprocessor architecture for Viterbi decoders with linear speedup.
IEEE Trans. Signal Process., 1993

Architectural tradeoffs for survivor sequence memory management in Viterbi decoders.
IEEE Trans. Commun., 1993

A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding.
Proceedings of the IEEE Data Compression Conference, 1993

1991
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up.
Proceedings of the 1991 International Conference on Acoustics, 1991


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