Fikret Dülger

Mahbuba Sheba Ullah

Socrates D. Vamvakos

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS.

[BibT_eX]

[DOI]

Oren E. Eliezer

IEEE J. Solid State Circuits, 2011

Spur-free all-digital PLL in 65nm for mobile phones.

[BibT_eX]

[DOI]

Sudheer K. Vemulapalli

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

Spurious free time-to-digital conversion in an ADPLL using short dithering sequences.

[BibT_eX]

[DOI]

Mahbuba Sheba

Fikret Dulger

Socrates D. Vamvakos

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2006

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process.

[BibT_eX]

[DOI]

Bertan Bakkaloglu

Paul Fontaine

Ahmed Nader Mohieldin

Solti Peng

Sher Jiun Fang

IEEE J. Solid State Circuits, 2006

A quad-band receiver for GSM/GPRS/EDGE in 90 nm digital CMOS.

[BibT_eX]

[DOI]

Sher Jiun Fang

Ahmed Nader Mohieldin

Paul Fontaine

Abdellatif Bellaouar

Michel Frechette

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2003

A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-μm CMOS.

[BibT_eX]

[DOI]

Fikret Dulger

Edgar Sánchez-Sinencio

José Silva-Martínez

IEEE J. Solid State Circuits, 2003

2002

Design trade-offs of a symmetric linearized CMOS LC VCO.

[BibT_eX]

[DOI]