Sujay Pandey

According to our database1, Sujay Pandey authored at least 9 papers between 2016 and 2021.

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Bibliography

2021
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.
Proceedings of the IEEE International Test Conference, 2020

2019
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.
Proceedings of the IEEE International Test Conference, 2019

2018
Error Resilient Neuromorphic Networks Using Checker Neurons.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Cross-Layer Control Adaptation for Autonomous System Resilience.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
DFM-aware fault model and ATPG for intra-cell and inter-cell defects.
Proceedings of the IEEE International Test Conference, 2017

2016
Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Noise-Resilient SRAM Physically Unclonable Function Design for Security.
Proceedings of the 25th IEEE Asian Test Symposium, 2016


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