Alodeep Sanyal

According to our database1, Alodeep Sanyal authored at least 22 papers between 2005 and 2017.

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Bibliography

2017
DFM-aware fault model and ATPG for intra-cell and inter-cell defects.
Proceedings of the IEEE International Test Conference, 2017

2014
Special session 12C: Young professionals in test - Town meeting.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Special session 11C: Young professionals in test - Elevator talks.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2013
Special session 12C: Town-hall meeting "young professionals in test".
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays.
IEEE Trans. Computers, 2012

2010
An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects.
IEEE Trans. Computers, 2010

BIST to Detect and Characterize Transient and Parametric Failures.
IEEE Des. Test Comput., 2010

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
An Improved Soft-Error Rate Measurement Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A study on impact of loading effect on capacitive crosstalk noise.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
On Composite Leakage Current Maximization.
J. Electron. Test., 2008

A Built-in Test and Characterization Method for Circuit Marginality Related Failures.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Built-In Self-Test Scheme for Soft Error Rate Characterization.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

On Accelerating Soft-Error Detection by Targeted Pattern Generation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

On Derating Soft Error Probability Based on Strength Filtering.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Accelerating Soft Error Rate Testing Through Pattern Selection.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
A Pattern Generation Technique for Maximizing Power Supply Currents.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
Dynamic power minimization during combinational circuit testing as a traveling salesman problem.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005


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