Suleyman Sair

According to our database1, Suleyman Sair authored at least 19 papers between 2000 and 2009.

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Bibliography

2009
Extending data prefetching to cope with context switch misses.
Proceedings of the 27th International Conference on Computer Design, 2009

2007
Two-level ata prefetching.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
An Evaluation of Deeply Decoupled Cores.
J. Instr. Level Parallelism, 2006

Long-term Performance Bottleneck Analysis and Prediction.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Improving the performance and power efficiency of shared helpers in CMPs.
Proceedings of the 2006 International Conference on Compilers, 2006

2005
Dynamically configurable shared CMP helper engines for improved performance.
SIGARCH Comput. Archit. News, 2005

Exploiting Intra-function Correlation with the Global History Stack.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Designing real-time H.264 decoders with dataflow architectures.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Low-Overhead Core Swapping for Thermal Management.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Creating Converged Trace Schedules Using String Matching.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003
A Decoupled Predictor-Directed Stream Prefetching Architecture.
IEEE Trans. Computers, 2003

Discovering and Exploiting Program Phases.
IEEE Micro, 2003

Phase Tracking and Prediction.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Catching Accurate Profiles in Hardwar.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
Pointer cache assisted prefetching.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Quantifying Load Stream Behavior.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2000
Predictor-directed stream buffers.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

DSPTune: A Performance Evaluation Toolset for the SHARC Signal Processor.
Proceedings of the Proceedings 33th Annual Simulation Symposium (SS 2000), 2000


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